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CMX8341 digital pmr (dpmr) b aseband processor ? datasheet advance information 8341 fi - 1.x dual - mode analogue pmr and digital pmr ( dpmr ) baseband processing features ? digital pmr ( dpmr ) baseband processor o dpmr (etsi ts 102 490) complian t o air interface physical layer (layer 1) o air interface data link layer (layer 2) o 4fsk modem ? soft - decision decoding ? afsd (automatic frame sync detection) ? auxiliary functions o 2 system clock outputs o tx pa ramp dac o 3 dacs, 4 inputs multiplexed to 2 adcs o gpio o t x enable and rx enable outputs ? half - duplex operation ? ralcwi vocoder o fully embedded implementation o no licensing or royalty payments o 3600bps over air data rate (2400bps voice plus 1200bps robust fec) o 4 - bit viterbi soft - decision decoding ? input from rf discr iminator ? 2 - point modulation drivers ? audio output with volume control ? microphone input ? low power operation ? lqfp packaging ? analogue pmr (legacy mode) o full audio band processing o sub - audio filtering o ctcss and dcs o 12.5 and 25khz channel filters application s ? built on firmasic ? technology o function image? 8341fi - 1.x required o serial memory or host loading o integration roadmap ? low cost digital pmr radios ? low cost digital pmr with legacy analogue pmr mode cml microcircuits communication semiconductors c interface c - bus external ref . clock power supplies rf section modulator discriminator pa ramp pll clocks gpio dacs mux adc cmx 8341 dpmr baseband processor rf interface auxiliary operations audio interface digital pmr air interface : physical , data link and control layer support data modem vocoder analogue pmr : core functionality system control serial memory ( optional ) external sub - audio
digital pmr (dpmr) baseband processor CMX8341 ? 1 brief description the 8341fi - 1.x function image? (fi) implements a half - duplex digital pmr processor including: 4fsk modem, a large proportion of the dpmr ? air interface; physical, data link and control layers, and an embedded low bit rate ralcwi vocoder (with no license or ro yalties required). in conjunction with a suitable host and a limiter/discriminator based rf transceiver, a compact, low cost, low power digital pmr radio conforming to etsis dpmr standard ts 102 490 can be realised. both isf and csf configurations are sup ported, including built - in support for bcd addressing modes. dual mode, analogue/digital pmr operation can also be achieved with the CMX8341 . the device is also compatible with etsis dpmr standard ts 102 658 for mode 1 operation. the embedded functionality of the CMX8341 , managing voice and data systems autonomously including the vocoder minimises host microcontroller interactions enabling the lowest operating power and t herefore the longest battery life for a dpmr radio. the CMX8341 utilises cmls proprietary firmasic ? component technology. on - chip sub - systems are configured by a function image?: this is a data file that is uploa ded during device initialisation and defines the device's function and feature set. the function image? can be loaded automatically from an external serial memory or host controller over the built - in c - bus serial interface. the device's functions and feat ures may be enhanced by subsequent function image? releases, facilitating in - the - field upgrades. this document refers specifically to the features provided by function image ? 8341 fi - 1.x. other features include two auxiliary adcs with four selectable inpu ts and four auxiliary dac interfaces (with an optional ramdac on the first dac output, to facilitate transmitter power ramping). the device has flexible powersaving modes and is available in the l8 (lqfp) package. this datasheet is the first part of a two - part document comprising datasheet and user manual: the user manual can be obtained by registering your interest in this product with your local cml representative. text in grey may be implemented in later versions of the function image ? 8341 fi - 1.x. dpmr is a registered trademark of the dpmr association
digital pmr (dpmr) baseband processor CMX8341 ? contents section page 1 brief description ................................ ................................ ................................ .. 2 1.1 history ................................ ................................ ................................ .............. 6 2 block diagram ................................ ................................ ................................ ...... 8 3 signal list ................................ ................................ ................................ ............. 9 3.1 signal definitions ................................ ................................ ........................... 12 4 exte rnal components ................................ ................................ ........................ 13 4.1 component value selection ................................ ................................ .......... 14 4.2 reference clock frequency ................................ ................................ .......... 14 4.3 serial memory connections ................................ ................................ ........... 15 4.4 other connections ................................ ................................ ......................... 15 4.5 autonomous signal routing ................................ ................................ .......... 16 5 general description ................................ ................................ ........................... 17 5.1 product features ................................ ................................ ........................... 17 5.1.1 dpmr features ................................ ................................ ....................... 17 5.1.2 analogue pmr features ................................ ................................ ......... 17 5.1.3 universal pmr functions ................................ ................................ ........ 18 5.1.4 au xiliary functions ................................ ................................ .................. 18 5.1.5 system interface ................................ ................................ ..................... 18 5.2 aspects of system design ................................ ................................ ............. 18 5.2.1 dpmr data transfer ................................ ................................ ............... 18 5.2.2 rssi measurement ................................ ................................ ................. 18 5.2.3 serial memory connection ................................ ................................ ...... 18 6 dpmr modem description ................................ ................................ ................ 19 6.1 modulation ................................ ................................ ................................ ..... 19 6.2 internal data processing ................................ ................................ ............... 21 6.3 frame sync detection and demodulation ................................ ..................... 22 6.4 fec and coding ................................ ................................ ............................ 25 6.5 voic e coding ................................ ................................ ................................ . 25 6.6 radio performance requirements ................................ ................................ 25 6.7 tone generator ................................ ................................ ............................. 25 7 analogue pmr description ................................ ................................ ............... 25 7.1 external sub - audio processing ................................ ................................ ..... 25 7.2 internal ctcss and dcs generation and detection ................................ .... 25 7.3 voice processing: ................................ ................................ .......................... 26 8 detailed descriptions ................................ ................................ ........................ 31 8.1 refere nce frequency ................................ ................................ .................... 31 8.2 host interface ................................ ................................ ................................ 31 8.2.1 c - bus operation ................................ ................................ .................... 31 8.3 function image ? loading ................................ ................................ ............. 33 8.3.1 fi loading from host controller ................................ .............................. 34 8.3.2 fi loading from an external serial memory ................................ ............ 36 8.4 device control ................................ ................................ ............................... 37 8.4.1 general notes ................................ ................................ ......................... 37 8.4.2 interrupt operatio n ................................ ................................ .................. 37
digital pmr (dpmr) baseband processor CMX8341 ? 8.4.3 signal routing ................................ ................................ ......................... 38 8.4.4 modem control ................................ ................................ ........................ 38 8.5 dpmr for matted operation ................................ ................................ .......... 39 8.5.1 tx mode ................................ ................................ ................................ .. 40 8.5.2 tx mode (prbs) ................................ ................................ ..................... 40 8.5 .3 rx mode ................................ ................................ ................................ .. 42 8.5.4 rx mode eye ................................ ................................ ........................... 43 8.5.5 rx mode pass - through ................................ ................................ ........... 44 8.5.6 sync mode ................................ ................................ .............................. 44 8.5.7 reset/abort ................................ ................................ ............................. 44 8.5.8 data transfer ................................ ................................ .......................... 44 8.5.9 vocoder section C pass - through mode ................................ .................. 45 8.5.10 vocoder section C noise gate ................................ ................................ 45 8.5.11 dpmr operating modes and addressing ................................ ................ 46 8.5.12 isf addressing ................................ ................................ ........................ 46 8.5.13 csf addressing ................................ ................................ ...................... 47 8.5.14 tx mo de (dpmr formatted) ................................ ................................ .... 47 8.5.15 rx mode (dpmr formatted) ................................ ................................ .... 49 8.5.16 slow data ................................ ................................ ................................ 50 8.6 analogue mode ................................ ................................ .............................. 51 8.6.1 tx mode analogue ................................ ................................ .................. 51 8.6.2 rx mode analogue ................................ ................................ .................. 51 8.7 squelch operation ................................ ................................ ......................... 51 8.8 gpio pin operation ................................ ................................ ....................... 51 8.9 auxiliary adc operation ................................ ................................ ................ 52 8.10 auxiliary dac/ramdac operation ................................ ............................... 52 8.11 digital system clock generators ................................ ................................ ... 53 8.11.1 m ain clock operation ................................ ................................ .............. 54 8.11.2 system clock operation ................................ ................................ ......... 54 8.12 signal level optimisation ................................ ................................ .............. 54 8.12.1 transmit path levels ................................ ................................ .............. 54 8.12.2 receive path levels ................................ ................................ ................ 55 8.13 tx spectrum plots ................................ ................................ ......................... 56 8.14 c - bus register summary ................................ ................................ ............. 58 9 performance specification ................................ ................................ ................ 59 9.1 electrical pe rformance ................................ ................................ .................. 59 9.1.1 absolute maximum ratings ................................ ................................ .... 59 9.1.2 operating limits ................................ ................................ ...................... 59 9.1.3 operating characteristics ................................ ................................ ........ 60 9.1.4 parametric performance ................................ ................................ ......... 66 9.2 operating characteristics C timing diagrams ................................ ............... 68 9.2.1 c - bus timing ................................ ................................ ......................... 68 9.3 packaging ................................ ................................ ................................ ...... 69
digital pmr (dpmr) baseband processor CMX8341 ? table page table 1 definition of power supply and reference voltages ................................ ........... 12 table 2 recommended component values ................................ ................................ .... 14 ta ble 3 dpmr frame format - call set - up, no ack ................................ ....................... 23 table 4 dpmr frame format - call set - up with ack ................................ ...................... 23 table 5 dcs codes and va lues ................................ ................................ ........................ 28 table 6 ctcss codes and values ................................ ................................ ................... 30 table 7 booten pin states ................................ ................................ ............................ 33 table 8 modem mode selection ................................ ................................ ...................... 39 table 9 modem control selection ................................ ................................ .................... 39 table 10 c - bus data registers ................................ ................................ ...................... 44 table 11 c - bus registers ................................ ................................ ............................... 58 figure page figure 1 block diagram ................................ ................................ ................................ ...... 8 figure 2 recommended external components ................................ ............................... 13 figure 3 serial memory connections ................................ ................................ ............... 15 figure 4 other conn ections ................................ ................................ ............................. 15 figure 5 tx routing C autonomous mode ................................ ................................ ....... 16 figure 6 rx routing C autonomous mode ................................ ................................ ....... 16 figure 7 4fsk prbs waveform - modulation ................................ ................................ . 20 figure 8 4fsk prbs waveform - spectrum ................................ ................................ ... 20 figure 9 dpmr modulation characteristics ................................ ................................ ...... 21 figure 10 internal data processing blocks ................................ ................................ ...... 22 figure 11 fs detection ................................ ................................ ................................ .... 24 figure 12 rx audio response ................................ ................................ ......................... 27 figure 13 tx audio response ................................ ................................ .......................... 27 figure 14 ctcss an d dcs filters ................................ ................................ .................... 28 figure 15 c - bus transactions ................................ ................................ ........................ 32 figure 16 fi loading from host ................................ ................................ ....................... 35 figure 17 fi loading from an external serial memory ................................ ..................... 36 figure 18 tx data flow ................................ ................................ ................................ .... 41 figure 19 rx data flow ................................ ................................ ................................ .... 43 figure 20 auxadc irq operation ................................ ................................ ................... 52 figure 21 digital clock generation schemes ................................ ................................ .. 53 figure 22 tx level adjustments (analogue) ................................ ................................ .... 55 figure 23 tx levels (digital) ................................ ................................ ............................ 55 figure 24 rx level adjustm ents (analogue) ................................ ................................ .... 56 figure 25 rx level adjustments (digital) ................................ ................................ ......... 56 figure 26 tx modulation spectra - 4800bps ................................ ................................ .... 57 figure 27 c - bus timing ................................ ................................ ................................ .. 68 figure 28 l8 mechanical outline: order as part no. CMX8341l8 ................................ .. 69 it is always recomme nded that you check for the latest product datasheet version from the datasheets page of the cml website: [www.cmlmicro.com].
digital pmr (dpmr) baseband processor CMX8341 ? 1.1 history version changes date 7 figure 9 updated to match latest etsi version 8.4.4 add text about analogue mode selection 8. 5.3 tx mode test added 8.5.5 rx mode dpmr added 8.5.6 rx mode raw added table 10 rx mode raw added 10.1.5 ramdac and dac2 tonegen updated to latest descriptions 10.1.10 add input invert bit $b0:b7 10.1.11 clarification to setting $b1:b1,0 10.1.20 rx raw mo de added, tx test mode (rep eated word for dpmr assoc. test modes) added 10.1.22 $c3 register description describes digital functions (as well as analogue), ramdac multiplier added 10.1.23 $c5 bit definitions corrected (matches 7131/7141fi - 1 and fi - 5) 10.1. 25 $c7:b7 (enable/disable vocoder control) added 10.1.24 add note on prog flag cleared in rx and tx modes 10.1.26 pass - through description updated 10.1.28 $ca bit definitions corrected (matches fi - 1 and fi - 5) 10.1.29 $cb bit definitions corrected (matches fi - 1 and fi - 5) 10.2.3 rx analogue pass - through added 28/01/14 6 pin 50 now connects to pin 49. figure 2 and pinout table corrected. correction of bit order in table 8. sync mode and rese t/abort descriptions added to 8.5. bit error and value to stop ramdac clarified in 10.1.5 bit settings clarified in 10.1.22 setting of p1.20 added to 10.2.2 bit settings clarified in 10.2.3 2 4 / 10 /12 5 rx pass - through mode added C this is advance information; changes and additions may be made to this specification. parameters marked tbd or left blank will be included in later issues. items that are highlighted or greyed out should be ignore d. these will be clarified in later issues of this
digital pmr (dpmr) baseband processor CMX8341 ? document. information in this advance document should not be relied upon for final product design.
digital pmr (dpmr) baseband processor CMX8341 ? 2 block diagram figure 1 block diagram booten 1 booten 2 refclk irqn rdata auxiliary functions cdata csn system clock outputs system clock 1 system clock 2 sysclk 1 sysclk 2 epsclk ssout epso epsi system control c - bus control interface sclk power supplies registers serial memory interface dvdd vdec dvss main clock pll boot control adc 1 adc 2 adc 3 adc 4 multiplexed adcs mux adc 1 thresholds averaging thresholds averaging adc 2 dacs dac 4 ramp profile ram gpioa gpiob gpio fi configured gpio dac 3 dac 2 dac 1 rxena txena gpio ( for atb 10 control ) dac 1 dac 2 dac 3 dac 4 signal inputs mod 1 audio mod 2 tx mod mode tx dpmr processing avdd vbias avss bias cvdd epscsn power control virqn mux vbias mic micfb vbias disc discfb vbias alt altfb filtering 4 fsk modem demodulator rx data buffer afsd soft - decision decoding dpmr payload decoding physical layer 1 data link layer 2 rx dpmr processing tx analogue pmr core operations rx analogue pmr audio processing voice filter de - scrambler de - emphasis expandor ctcss / dcs decoder sub - audio filter audio processing agc voice filter compressor pre - emphasis scrambler channel filter limiter sub - audio filter ctcss / dcs encoder ralcwi vocoder ( decoder ) filtering 4 fsk modem modulator tx data buffer data packet assembly dpmr payload encoding physical layer 1 data link layer 2 ralcwi vocoder ( encoder ) signal outputs cmx 8341 dpmr baseband processor sub - audio
digital pmr (dpmr) baseband processor CMX8341 ? 3 signal li st CMX8341 l8 pin description pin no. name type 1 gpiob ip + pu or op general - purpose input/output. 3 sysclk1 op synthesised digital system clock output 1 7 txena op tx enable C each of the two adc blocks can select its inp ut signal from any one of these input pins, or from the mic, alt or disc input pins. see section 8.9 for details. 30 auxadc2 ip auxiliary adc input 2 33 auxadc3 ip auxiliary adc input 3 34 auxadc4 ip auxiliary adc input 4 36 auxdac1 op auxiliary dac output 1 37 auxdac2 op auxiliary dac output 2 41 - - connect to pin 11 42 auxdac3 op auxiliary dac output 3 48 auxdac4 op auxiliary dac output 4 / filtered sub - audio output 50 sync bi sync output. c onnect to pin 49. 54 - - connect to pin 56 55 refclk ip input from the external clock source 56 - - connect to pin 54
digital pmr (dpmr) baseband processor CMX8341 ? CMX8341 l8 pin description pin no. name type 59 cdata ip c - bus command data: serial data input from the c. 61 rdata t/s c - bus reply data: a 3 - state c - bus serial data output to the c. this output is h igh impedance when not sending data to the c. 62 ssout op serial memory interface C chip select. connect to pin 92 64 resetn ip vocoder section general reset (active low, no pullup) 69 sclk ip c - bus serial clock: the c - bus serial clock input from the c. 71 sysclk2 op synthesised digital system clock output 2 73 csn ip c - bus chip select: the c - bus chip select input from the c - there is no internal pullup on this input (active low). 76 epsi op serial memory interface C data output from CMX8341 78 epsclk op serial memory interface C clock 81 epso ip + pd serial memory interface C data input to CMX8341 83 epscsn op serial memory interface C memory select (active lo w) 84 booten1 ip + pd used in conjunction with booten2 to determine the operation of the bootstrap program. 86 - - connect to pin 78 (epsclk) 87 booten2 ip + pd used in conjunction with booten1 to determine the operation of the bootstrap program. 88 - - connect to pin 76 (epsi) 90 - - connect to pin 81 (epso) 91 irqn op c - bus interrupt request: a 'wire - orable' output for connection to the interrupt request input of the c. pulled down to dv ss when active and is high impedance when inactive. an externa l pull - up resistor (r1) is required. 92 - - connect to pin 62 (ssout) 93 virqn op connect a n external pull - up resistor (r2) to dvdd 97 rxena op rx enable C active low when in rx mode. 98 gpioa ip + pu or op general - purpose input/output.
digital pmr (dpmr) baseband processor CMX8341 ? CMX8341 l8 pin description pin no. name type power supplies and no connections 32, 47, 57, 60, 66, 70, 72, 74, 94 dvdd pwr dv dd : digital +3.3v supply rail. this pin should be decoupled to dv ss by capacitors mounted close to the device pins. 53, 95 vdec pwr v dec : internally generated 2.5v supply voltag e. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections allowed. 31, 96 cvdd pwr digital core +1.8v supply rail. this pin should be decoupled to dv ss by capacitors mounted close to the device pins. 4, 6, 44, 49, 51, 52, 63, 65, 68, 85, 89, 100 dvss pwr dv ss : negative digital supply 5, 9, 17, 19, 21, 40 avss pwr av ss : negative analogue supply 2, 14, 26,35 avdd pwr av dd : analogue +3.3v supply rail. levels and thresholds within the device are proportional to thi s voltage. this pin should be decoupled to av ss by capacitors mounted close to the device pins. 8 vbias pwr internally generated bias voltage of about av dd /2, except when the device is in powersave mode when voltage on vbias pin will discharge to av ss . must be decoupled to av ss by a capacitor mounted close to the device pins. no other connections allowed. do not connect to bias pin. 27 bias pwr internally generated bias voltage of about av dd /2, except when the device is in powersave mode when voltage on bias pin will discharge to av ss . must be decoupled to av ss by a capacitor mounted close to the device pins no other connections allowed. do not connect to vbias pin. 38, 39, 43, 45, 46, 58, 67, 75, 77, 79, 80, 82, 99 n/c nc do not make any connection to this pin notes: ip = input ip + pu = input with internal pullup resistor ip + pd = input with internal pulldown resistor op = output bi = bidirectional digital signal t/s = 3 - state digital output pwr = power supply nc = no connection
digital pmr (dpmr) baseband processor CMX8341 ? 3.1 signal definitions table 1 definition of power supply and reference voltages signal name pins usage av dd avdd 3.3v power supply for analogue circuits dv dd dvdd 3.3v power supply for digital circuits dv core cvdd 1.8v power supply for digital circuits v dec vdec 2.5v internally - derived power supply for digital circuits v bias vbias, bias 1.65v internally - derived power supply for analogue circuits av ss avss ground for all analogue circuits dv ss dvss ground for all digital circu its
digital pmr (dpmr) baseband processor CMX8341 ? 4 external components figure 2 recommended external components to achieve good noise performance, v dd decoupling is very important. it is recommended that the printed circuit board is laid out with analogue and digital gr ound planes in the CMX8341 area to provide a low impedance connection between the v ss pins and the v dd decoupling capacitors. 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 1 75 98 analogue ground analogue ground plane digital ground plane digital ground CMX8341l8 c6 c7 c5 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c32 c19 r3 r2 r1 d1 av ss dv ss dv dd dv core v d e c d v d d c s n d v d d s y s c l k 2 d v d d s c l k d v s s d v d d d v s s r e s e t n s s o u t r d a t a d v d d c d a t a n / c d v d d r e f c l k a v s s t x e n a v b i a s a v s s d i s c d i s c f b a v d d a l t a l t f b a v s s m i c f b a v s s m i c a v s s o u t p m o d 1 m o d 2 o u t n d v s s s y s c l k 1 a v d d g p i o b d v s s dvss epsi epsclk epso epscsn booten1 t o s e r i a l m e m o r y dvss booten2 dvss irqn virqn dvdd vdec cvdd rxena gpioa dvss auxdac4 dvdd dvss auxdac3 avss auxdac2 auxdac1 avdd auxadc3 dvdd cvdd auxadc1 bias avdd auxadc2 auxadc4 av dd n/c n/c n/c n/c n/c sync n/c n/c n/c n/c n/c audio n / c n / c d v s s d v s s d v s s dv core 1.8v dv core 1.8v dv dd 3.3v dv dd 3.3v dv dd 3.3v av dd 3.3v v dec 2.5v v bias 1.65v v dec 2.5v cdata rdata csn sclk irqn c - b u s booten1 booten2 b o o t c o n t r o l refclk resetn sync m i s c e l l a n e o u s rxena auxadc1-4 auxdac1-4 a u x i l i a r y s i g n a l s txena gpioa sysclk1 sysclk2 gpiob v bias 1.65v
digital pmr (dpmr) baseband processor CMX8341 ? table 2 recommended component values r1 100k r9 100k c1 n/f c8 10nf c16 100nf c24 100pf r2 100k r10 100k c2 n/f c9 10f c17 10f c25 100pf r3 470k r11 22k c3 n/f c10 10nf c18 10nf c26 470pf r4 10k r12 100k c4 n/f c11 1.0f c19 100nf c27 470pf r5 100k r13 22k c 5 100nf c12 10nf c20 1.0f c28 100pf r6 100k r14 100k c6 10f c13 10nf c21 1.0f c29 100pf r7 100k d1 1n4148 c7 10nf c14 10f c22 n/f c30 1.0f r8 100k tg1 ts5a459dbvr c15 100nf c23 100pf c31 1.0f c32 100nf resistors ? 5%, capacitors and inductors ? 20% unless otherwise stated. please also refer to figure 4 . 4.1 component value selection 1. r7 should be selected to provide the desired dc gain of the discriminator input, as follows: ? gain disc ? = 100k ? / r7 2. the gain should be such that the resultant output at the discfb pin is within the disc input signal range specified in 8.12.2 . for 4fsk modulation, this signal should be dc coupled from the limiter/ discrimi nator output. 3. r6 should be selected to provide the desired dc gain (assuming c21 is not present) of the alternative input as follows: ? gain alt ? = 100k ? / r6 4. the gain should be such that the resultant output at the altfb pin is within the alternative input signal range specified in 8.12 . 5. r5 should be selected to provide the desired dc gain (assuming c20 is not present) of the microphone input as follows: ? gain mic ? = 100k ? / r5 6. the gain should be such that the resu ltant output at the micfb pin is within the microphone input signal range specified in 8.12.1 . for optimum performance with low signal microphones, an additional external gain stage may be required. 7. c21 and c20 should be selected to maintain the lower frequency roll - off of the mic and alt inputs as follows: c21 ? 1.0f ? ? gain alt ? c20 ? 30nf ? ? gain mic ? 8. alt and altfb connections allow the user to have a second discriminator, microphone input or external sub - audi o signalling source. component connections and values are as for the respective disc and mic networks. if this input is not required, the alt pin should be connected to av ss . 9. audio output is only used in the function image tm 8341fi - 1.x when analogue audi o functions are selected. the outp digital audio output is passed through a transmission gate (tg1), so that it can be turned off when digital mode is not selected. 4.2 reference clock frequency the function image tm 8341 fi - 1.x is designed to work with an ex ternal reference clock source of 19.2mhz, connected to the refclk pin.
digital pmr (dpmr) baseband processor CMX8341 ? 4.3 serial memory connections connections for a typical 512kbyte serial memory are shown below: figure 3 serial memory connections 4.4 other connections figure 4 other connections a t 2 5 f 5 1 2 a n - 1 0 s h - 2 . 7 c m x 8 3 4 1 l 8 r 4 epsi so epso sck epsclk csn epscsn holdn wpn jumper dv dd dv ss si c m x 8 3 4 1 l 8 micfb mic altfb alt discfb c 25 r 10 r 7 disc mic r 9 r 6 c 24 c 21 r 8 r 5 c 23 c 20 alt disc c m x 8 3 4 1 l 8 outp mod 2 mod 1 audio r 11 r 12 r 13 r 14 c 26 c 28 c 29 c 27 c 31 c 30 av ss spkr mod 1 mod 2 ctrl tg 1
digital pmr (dpmr) baseband processor CMX8341 ? 4.5 autonomous signal routing figure 5 tx routing C autonomous mode figure 6 rx routing C autonomous mode mux core baseband processing mux ralcwi vocoder mic disc alt mod 1 mod 2 audio dpmr analogue mode ext sub - audio dpmr modem analogue processing mux core baseband processing mux ralcwi vocoder mic disc alt mod 1 mod 2 audio dac 4 dpmr analogue mode ext sub - audio dpmr modem analogue processing
digital pmr (dpmr) baseband processor CMX8341 ? 5 general description a block diagram of the device is shown in figure 1 . a flexible power control facility allows the device to be placed in its optimum powersa ve mode when not actively processing signals. the device includes a reference clock input and provides 2 x pll system clock outputs for general use, if required. 5.1 product features 5.1.1 dpmr features the 8341fi - 1.x function image ? is intended for use in half dupl ex digital pmr equipment using 4fsk modulation at 4800bps suitable for 6.25khz channel systems. complete dpmr baseband processing is provided, including the ralcwi vocoder function. much of the dpmr etsi ts 102 490 standard air interface protocol is embedd ed in the 8341fi - 1.x function image ? operation namely: air interface physical layer 1 ? 4fsk modulation and demodulation ? bit and symbol definition ? frequency and symbol synchronisation ? transmission burst building and splitting air interface data link layer 2 ? channel coding (fec, crc) ? interleaving, de - interleaving and bit ordering ? frame and superframe building and synchronising ? burst and parameter definition ? link addressing (source and destination) ? interfacing of voice applications (voice data) with the physica l layer ? data bearer services ? exchanging signalling and/or user data with the call control layer ? automatic own - id and group - id detection 5.1.2 analogue pmr features the device provides legacy analogue pmr operation including: ? complete voice processing ? 300hz hpf ? 1 2.5khz channel filter ? 25khz channel filter ? hard limiter with anti - splatter filter ? compandor ? scrambler ? voice agc ? level adjust ? inband tone generation ? external sub - audio filtering ? internal sub - audio (ctcss and dcs) generation and detection
digital pmr (dpmr) baseband processor CMX8341 ? the selection of th ese analogue processing modes is controlled by the analogue mode bits in the modem control register, $c1:b15 - 8. 5.1.3 universal pmr functions these include: ? ramdac operation ? txenable (txena) and rx enable (rxena) hardware signals ? two - point modulation outputs ? har d or soft data output options ? embedded ralcwi vocoder 5.1.4 auxiliary functions ? two programmable system clock outputs ? two auxiliary adcs with four selectable external input paths ? four auxiliary dacs, one with built - in programmable ramdac ? gpio pins 5.1.5 system interfa ce ? optimised c - bus (4 - wire high - speed synchronous serial command/data bus) interface to host for control and data transfer ? open drain irq to host ? serial memory boot mode ? c - bus (host) boot mode 5.2 aspects of system design 5.2.1 dpmr data transfer when transmitting, an initial block of payload or control channel data will need to be loaded from the host into the c - bus txdata registers. the CMX8341 can then format and transmit that data while at the same time loading in the following data blo cks from the host or the vocoder section. when receiving, the host needs to consider that when a signal is received over the air there will be a processing delay while the CMX8341 filters, demodulates and decodes the output data before presenting it to the host or the vocoder section. for the best performance, voice payload data can be output in soft - decision (4 - bit log - likelihood ratio) format, compatible with the vocoder section, although this mode increases the data transfer ra te over c - bus by a factor of four. 5.2.2 rssi measurement the auxadc provided by the CMX8341 can be used to detect the squelch or rssi signal from the rf front - end while the device is in rx or idle mode. this allows a significant degre e of powersaving within the CMX8341 and avoids the need to wake the host up unnecessarily. the host programmable auxadc thresholds allow for user selection of squelch threshold settings. 5.2.3 serial memory connection a serial memory i nterface with a dedicated chip select pin (epscsn) connects the external serial memory, which may be used to hold the contents of the function image?, to the CMX8341 .
digital pmr (dpmr) baseband processor CMX8341 ? 6 dpmr modem description this modem is set to run at 4800bps, occupying a 6.25khz bandwidth rf channel. it has been designed such that, when combined with suitable rf, host controller and appropriate control software, it meets the requirements of the en 301 166 standards. see www.e tsi.org for details of these standards. ts 102 490 is available on the etsi web site ( www.etsi.org ), which describes a 6.25khz channel spacing fdma dpmr system. this standard uses a 4fsk modulation scheme with an over - air bit rate of 4800bps (ie. 2400 symbols per second). with respect to dpmr formatted modes of operation, this document should be read in conjunction with the etsi standard. the dpmr standard does not specify a voice coding algorithm: the ralcwi vocoder i n the CMX8341 is suitable for this purpose. version 1.5.1 of ts 102 490 section 5.16 introduces two additional vocoder control bits which specify which vocoder is in use for a particular voice call. these additional bits are supp orted by the 8341fi - 1.x function image ? and should be set appropriately by the host. these have been further defined by the dpmr association as: version vocoder ======= ======= 00 ambe+2 01 to be selected by chinese dra 10 ralcwi 1 1 manufacturer defined 6.1 modulation the dpmr 4fsk modulation scheme as defined in ts 102 490 section 12 operates in a 6.25khz channel bandwidth with a deviation index of 0.29 and has an over - air bit rate of 4800bps (2400 symbols per second). rrc filters ar e implemented in both tx and rx with a filter alpha of 0.2. the maximum frequency error is +/ - 625hz and the CMX8341 can adapt to the maximum time - base clock drift of 2ppm over the duration of a 180 - second burst. figure 9 shows the basic parameters of the 4fsk modulation, symbol mapping and filtering requirements. figure 7 and figure 8 show a transmitted prbs waveform, as recorded on a spectrum analyser in 36k span and zero - span mode, having been two - point modulated using a suitable rf transmitter.
digital pmr (dpmr) baseband processor CMX8341 ? figure 7 4fsk prbs waveform - modulation figure 8 4fsk prbs waveform - spectrum r e f l v l 3 0 d b m 3 0 d b m r e f l v l 3 0 d b m 3 0 d b m 3 0 d b o f f s e t a s t a r t 0 s s t o p 3 5 m s c f 4 4 6 . 1 m h z d e m o d b w : 1 0 0 k h z r e a l t i m e o f f a f - s i g n a l f m [ h z ] 5 0 0 1 v i e w - 2 k - 1 . 5 k - 1 k - 5 0 0 0 5 0 0 1 k 1 . 5 k 2 k - 2 . 5 k 2 . 5 k 1 m a r k e r 1 [ t 1 ] 3 1 . 3 9 9 1 8 m s f m 6 6 1 . 9 8 7 h z 1 [ t 1 ] 3 1 . 3 9 9 1 8 m s f m 6 6 1 . 9 8 7 h z d 1 1 . 0 5 k h z d 2 - 1 . 0 5 k h z d a t e : a r b w 1 0 0 h z v b w 1 k h z s w t 1 8 s u n i t d b m 1 r m 3 0 . 8 d b o f f s e t r e f l v l 3 0 d b m r e f l v l 3 0 d b m r f a t t 2 0 d b 3 . 6 k h z / c e n t e r 4 4 6 . 1 m h z s p a n 3 6 k h z - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 - 7 0 3 0 1 m a r k e r 1 [ t 1 ] 1 6 . 4 8 d b m 4 4 6 . 1 0 0 1 0 8 2 2 m h z 1 [ t 1 ] 1 6 . 4 8 d b m 4 4 6 . 1 0 0 1 0 8 2 2 m h z c h p w r 2 7 . 5 3 d b m a c p u p - 6 6 . 5 5 d b a c p l o w - 6 7 . 1 4 d b a l t 1 u p - 7 9 . 4 5 d b a l t 1 l o w - 8 0 . 2 1 d b c u 2 c u 2 c u 1 c u 1 c l 1 c l 1 c l 2 c l 2 c 0 c 0 d a t e :
digital pmr (dpmr) baseband processor CMX8341 ? figure 9 dpmr modulation characteristics 6.2 internal data processing the CMX8341 operates as a half - duplex device, either receiving signals from the rf circuits in rx mo de, or sourcing signals to the rf circuits in tx mode. it also has a low power idle mode to support battery saving protocols. the internal data processing blocks for tx and rx modes are illustrated in figure 10 . 0 ? f < (1 - ) / 2t h( f ) = cos[(t / 4)(2 f -( 1 - )/ t] (1 + ) / 2t ? f (1 - ) / 2t ? f < (1 + ) / 2t , , , 1 0 = 0.2 t = 1/2400 *tx baseband filter frequency modulator 4fsk output information bits input h( f ) filter 4 fsk deviation di-bit symbol deviation 01 2 +3 +1 050hz +350hz -350hz -1050hz +1 -1 -3 00 2 10 2 11 2 *rx baseband filter frequency demod fm if signal h( f ) filter d( f ) filter information bits output 0 ? f < (1 - ) / 2t h( f ) = cos[(t / 4)(2 f -( 1 - )/ t] (1 + ) / 2t ? f (1 - ) / 2t ? f < (1 + ) / 2t , , , 1 0 d( f ) = sin ( f t ) f t = 0.2 t = 1/2400
digital pmr (dpmr) baseband processor CMX8341 ? figure 10 internal data processing blocks 6.3 frame sync detection and demodulation the analogue signal from the limiter/discriminator of the external rf section should be applied to one of the CMX8341 inputs (normally the disc input) where it can be adjusted to the correct level either by selection of the feedback resistor or using the CMX8341 input gain settings. the signal is filtered using a root - raised cosine filter and inverse rx sinc filter matching the filters applied in the transmitter, then passed to the afsd (automated frame sync detector) block which extracts symbol and frame synchronisation. during this process the 4fsk demod ulator and the following data - processing sections are dormant to minimise power consumption. when frame synchronisation has been achieved the afsd section is powered down, and timing and symbol - level information is passed to the 4fsk demodulator which star ts decoding the subsequent data bits. the CMX8341 can detect the end of a call by scanning the received control channel fields and will automatically disable the demodulator and restart frame sync search when requ ired without host intervention. a dpmr call begins with a 72 - bit ( or longer ) preamble sequence followed by an 80ms header frame, which contains a 48 - bit frame sync (fs1 or fs4). subsequent payload frames contain either a 24 - bit frame sync (fs2) or a 24 - bit colour code. the CMX8341 can scan for all dpmr frame syncs concurrently. it uses fs1 to detect the start of a transmission and this is reported to the host by setting the fs1 detect bit in the irq status register . it can also optionally use fs2 to perform a late entry into an existing call, reported by setting the fs2 detect bit. the short length of fs2 gives a higher probability of false detections, so by default the CMX8341 will only generate an fs2 detect if two successive fs2 frame syncs are detected at the correct frame spacing in the received signal. the frame syncs and preamble defined in ts 102 490 are always used. when frame synchronisation has been achieved and the 4fsk demodulator is enabled, frame sync detection is switched off and any subsequent frame sync sequences embedded in the received data are not reported to the host. c - bus port data buffer frame type detect fec interleave scramble packet formatter data router vocoder 4 - fsk modulator filter i / q look - up mux filter afsd 4 - fsk demod frame type detect de - interleave de - scramble de - fec data router vocoder data buffer address matcher c - bus port packet de - formatter disc input mod 1 output mod 2 output control info control info voice data voice data vocoder input
digital pmr (dpmr) baseband processor CMX8341 ? table 3 dpmr frame format - call set - up, no ack table 4 dpmr frame format - call set - up with ack bit no. 24 48 72 96 120 144 168 192 216 240 264 288 312 336 360 384 press ptt header tx cc frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload tx repeat frames 1 to 4 until ptt released. end tx fs3 header info 1 header info 0 end flag preamble fs1 bit no. 24 48 72 96 120 144 168 192 216 240 264 288 312 336 360 384 press ptt header tx cc end tx fs3 ack rx cc header tx cc frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload tx repeat frames 1 to 4 until ptt released. end tx fs3 header info 1 header info 0 end flag preamble fs1 header info 0 preamble fs1 header info 1 end flag preamble fs1 header info 0 header info 1
digital pmr (dpmr) baseband processor CMX8341 ? figure 11 fs detection rx enabled afsd active 4 fsk dormant fs 1 detected ? afsd off 4 fsk active irq fs 1 fs 2 detected ? afsd off 4 fsk active irq fs 2 demodulate demodulate irq fs 2 cc detected ? fs 2 detected ? id & cc matched ? irq called irq datardy ( hdr + le ) enable vocoder transfer data to vocoder end detected ? irq datardy ( end ) no no no no no no id & cc matched ? no process data afsd process analyse cch data decode , de - interleave analyse hdr data decode , de - interleave irq called irq datardy ( hdr ) disable vocoder
digital pmr (dpmr) baseband processor CMX8341 ? 6.4 fec and coding the CMX8341 imp lements all crcs, hamming codes, interleaving and scrambling required by the dpmr standard. crc failures in control channel fields and coded data blocks are indicated to the host by issuing an event irq with a corresponding error code in the modem status register, $c9. this relieves the host of a substantial processing load and has the added advantage of reducing the complexity and timing constraints of interfacing between the host and the CMX8341 . the dpmr header frame format c ontains duplicate copies of all control channel fields (in the hi0 and hi1 header information blocks) but only one decoded copy of each field will be presented back to the host. on receiving a header frame, the CMX8341 decodes bo th hi blocks, checks crcs and can accept the call if either block is valid (the other hi block is discarded). 6.5 voice coding the CMX8341 contains a ralcwi vocoder. the CMX8341 uses the serial memory inter face port (shared with the boot serial memory) to issue control commands and transfer voice payload data directly to the vocoder section. voice data transferred to the vocoder section in rx mode always uses soft decision (4 - bit log - likelihood ratio) format . this option is also available for voice payload data routed to the host (tx mode), although it increases the required data transfer rate over c - bus by a factor of four. 6.6 radio performance requirements the CMX8341 demodulator is designed to process a 4fsk signal from a limiter / discriminator source. for optimum performance the signal should not be significantly degraded by filters that are excessively narrow and / or cause significant group delay distortion. care should be taken in i nterfacing the device to the radio circuits to maintain the frequency and phase response (both low and high end), in order to achieve optimum performance. test modes are provided to assist in both the initial design and production set - up procedures. furthe r information and application notes can be found at http://www.cmlmicro.com . 6.7 tone generator this allows the user to generate audio tones in the range 300hz to 3khz. it will default to 1khz. a separate level control is provided. c - bus register $c3 is available for setting the tone frequency (shared with other functions). 7 analogue pmr description 7.1 external sub - audio processing an external sub - audio processing path is available for the host to generate or detect sub - a udio tones. in tx, sub - audio tones applied to the alt input are filtered and then summed with the in - band signal and presented to the mod1 and mod2 outputs. in rx, the sub - audio tones are separated by filters from the received signal applied to the disc in put. the sub - audio signal is then routed to the auxiliary dac4 output. the filter used in the path can be set by the programming register, either a 260hz chebyshev suitable for ctcss or a 150hz 4 - pole bessel for dcs. 7.2 internal ctcss and dcs generation and detection an internal generator/detector is available for the 51 ctcss tones shown in table 6 and the 83 dcs codes shown in tab le 5 . squelch - tail elimination is provided by inverting the mod outputs in ct css mode or a 134hz turn - off tone in dcs mode. the tone/code to be generated is set by the value in the auxdata/sub - audio write register ($c2) in tx mode and read from the auxdata/sub - audio read register ($cc) in rx mode (see section 10.1.30 ). the use of the internal generator/detector is determined by program block p2.0 b5 and b4 (see section 10.2.3 ).
digital pmr (dpmr) baseband processor CMX8341 ? 7.3 voice processing: a set of audio processing blocks are available for use in analogue mode: ? 300h z hpf ? 12.5khz channel filter or 25khz channel filter ? hard limiter with anti - splatter filter ? compandor ? scrambler ? voice agc ? level adjust ? in - band audio generator/s in both rx and tx paths the 12.5khz channel filter will be selected by default, the 25khz filte r can be enabled by setting p2.0:b0. note that in analogue mode, the digital mode output of the vocoder section should be isolated using an external analogue switch (see figure 4 ). 300hz hpf this is designed to reject signals belo w 300hz from the voice path so that sub - audio signalling can be inserted (in tx) or removed (in rx) as appropriate. it should be enabled whenever sub - audio signalling is required. 12.5khz/25khz channel filters these are designed to meet the requirements of etsi en 300 296 for voice signal processing and feature an upper roll - off at 2.55 and 3.0khz respectively. hard limiter this is provided to limit the peak deviation of the radio signal to meet the requirements of etsi en 300 296. an anti - splatter filter i s included to reduce the effects of any harmonic signals generated in the process. the limiter threshold can be set using p2.3. compander a syllabic compressor/expander is provided, similar to that used in the 7031/7041 - fi - 1.x to increase the dynamic range of the voice signal. the unity gain points for tx and rx can be set independently using p2.9 and p2.10. scrambler a frequency inversion scrambler is provided to enable a basic level of privacy. the default inversion frequency is 3300hz, but can be program med using $cd:1001 b , however some loss of signal at the band edges may occur due to the channel filter roll - off. voice agc an automatic gain control system is provided in the voice path, utilising the programmable gain settings of the input 1 amplifier. wh en used in conjunction with the hard limiter function, this can compensate for large variations in the mic input signal without introducing significant distortion. the agc threshold is programmable using p21. whilst the maximum gain setting and the decay t ime can be set using p2.2. when this feature is enabled, the host should not attempt to directly control the input 1 gain setting. level adjust independent level adjustments are provided using $c3 register for the voice, in - band and sub - audio signals, see section 8.12 for further details.
digital pmr (dpmr) baseband processor CMX8341 ? figure 12 rx audio response figure 13 tx audio response 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) $c1=$8301, narrow $c1=$8301, wide template 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) $c1=$8302, narrow $c1=$8302, wide template
digital pmr (dpmr) baseband processor CMX8341 ? figure 14 ctcss and dcs filters tab le 5 dcs codes and values register value register value dcs code true inverted dcs code true inverted decimal hex decimal hex decimal hex decimal hex no code 0 00 100 64 311 42 2a 142 8e 23 1 01 101 65 315 43 2b 14 3 8f 25 2 02 102 66 331 44 2c 144 90 26 3 03 103 67 343 45 2d 145 91 31 4 04 104 68 346 46 2e 146 92 32 5 05 105 69 351 47 2f 147 93 43 6 06 106 6a 364 48 30 148 94 47 7 07 107 6b 365 49 31 149 95 51 8 08 108 6c 371 50 32 150 96 54 9 09 109 6d 411 51 33 151 97 65 10 0a 110 6e 412 52 34 152 98 71 11 0b 111 6f 413 53 35 153 99 72 12 0c 112 70 423 54 36 154 9a 73 13 0d 113 71 431 55 37 155 9b 74 14 0e 114 72 432 56 38 156 9c 114 15 0f 115 73 445 57 39 157 9d 115 16 10 116 74 464 5 8 3a 158 9e 116 17 11 117 75 465 59 3b 159 9f 125 18 12 118 76 466 60 3c 160 a0 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) $c1=$a302, dcs template $c1=$a302, ctcss
digital pmr (dpmr) baseband processor CMX8341 ? register value register value dcs code true inverted dcs code true inverted decimal hex decimal hex decimal hex decimal hex 131 19 13 119 77 503 61 3d 161 a1 132 20 14 120 78 506 62 3e 162 a2 134 21 15 121 79 516 63 3f 163 a3 143 22 16 122 7a 532 64 40 164 a4 152 23 17 123 7b 546 65 41 165 a5 155 24 18 124 7c 565 66 42 166 a6 156 25 19 125 7d 606 67 43 167 a7 162 26 1a 126 7e 612 68 44 168 a8 165 27 1b 127 7f 624 69 45 169 a9 172 28 1c 128 80 627 70 46 170 aa 174 29 1d 129 81 631 71 47 171 ab 205 30 1e 130 82 632 72 48 172 ac 223 31 1f 131 83 654 73 49 173 ad 226 32 20 132 84 662 74 4a 174 ae 243 33 21 133 85 664 75 4b 175 af 244 34 22 134 86 703 76 4c 176 b0 245 35 23 135 87 712 77 4d 177 b1 251 36 24 136 88 723 78 4e 178 b2 261 37 25 137 89 731 79 4f 179 b3 263 38 26 138 8a 732 80 50 180 b4 265 39 27 139 8b 734 81 51 181 b5 271 40 28 140 8c 743 82 52 182 b6 306 41 29 141 8d 754 83 53 183 b7 user defined 84 54 184 b8
digital pmr (dpmr) baseband processor CMX8341 ? table 6 ctcss codes and values register value ctcs s tone register value ctcss tone decimal hex frequency decimal hex frequency 200 c8 no tone 228 e4 173.8 201 c9 67.0 229 e5 179.9 202 ca 71.9 230 e6 186.2 203 cb 74.4 231 e7 192.8 204 cc 77.0 232 e8 203.5 205 cd 79.7 233 e9 210.7 206 ce 82. 5 234 ea 218.1 207 cf 85.4 235 eb 225.7 208 d0 88.5 236 ec 233.6 209 d1 91.5 237 ed 241.8 210 d2 94.8 238 ee 250.3 211 d3 97.4 239 ef 69.3 212 d4 100.0 240 f0 62.5 213 d5 103.5 241 f1 159.8 214 d6 107.2 242 f2 165.5 215 d7 110.9 243 f3 1 71.3 216 d8 114.8 244 f4 177.3 217 d9 118.8 245 f5 183.5 218 da 123.0 246 f6 189.9 219 db 127.3 247 f7 196.6 220 dc 131.8 248 f8 199.5 221 dd 136.5 249 f9 206.5 222 de 141.3 250 fa 229.1 223 df 146.2 251 fb 254.1 224 e0 151.4 252 fc user defined 225 e1 156.7 253 fd --- 226 e2 162.2 254 fe dcs turn - off 227 e3 167.9 255 ff invalid tone
digital pmr (dpmr) baseband processor CMX8341 ? 8 detailed descriptions 8.1 reference frequency this device is suitable for use with a 19.2mhz external frequency source only. 8.2 host interface a serial dat a interface (c - bus) is used for command, status and data transfers between the CMX8341 and the host c; this interface is compatible with microwire and spi. interrupt signals notify the host c when a change in status has occurre d and the c should read the status register across the c - bus and respond accordingly. interrupts only occur if the appropriate mask bit has been set. see section 8.4.2 . the CMX8341 will monitor the s tate of the c - bus registers that the host has written - to every 250s (the c - bus latency period) hence it is not advisable for the host to make successive writes to the same c - bus register within this period. 8.2.1 c - bus operation this block provides for the tran sfer of data and control or status information between the CMX8341 s internal registers and the host c over the c - bus serial interface. each transaction consists of a single address byte sent from the c which may be followed by one or more data byte(s) sent from the c to be written into one of the CMX8341 s write only registers, or one or more data byte(s) read out from one of the CMX8341 s read only registers, as shown in figure 15 . data sent from the c on the cdata (command data) line is clocked into the CMX8341 on the rising edge of the sclk (serial clock) input. rdata (reply data) sent from the CMX8341 to the c is valid when the sclk is high. the csn line must be held low during a data transfer and kept high between transfers. the c - bus interface is compatible with most common c serial interfaces. the number of data bytes following an addres s byte is dependent on the value of the address byte. the most significant bit of the address or data is sent first. for detailed timings see section 9.2.1 . note that, due to internal timing constraints, there may be a delay of up to 250s between the end of a c - bus write operation and the device reading the data from its internal register.
digital pmr (dpmr) baseband processor CMX8341 ? c - bus write: see note 1 see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 7 6 0 7 0 msb lsb msb lsb msb lsb address/command byte upper 8 bits lower 8 bits rdata high z state c - bus read: see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 msb lsb address byte upper 8 bits lower 8 bits rdata 7 6 0 7 0 high z state msb lsb msb lsb data value unimportant repeated cycles either logic level valid (and may change) either logic level valid (but must not change from low to high) figure 15 c - bus transactions notes: 1. for command byte transfers only the first 8 bits are transferred ($01 = reset). 2. for single byte data transfers only the first 8 bits of the data are transferred. 3. the cdata and rdata lines are never active at the sa me time. the address byte determines the data direction for each c - bus transfer. 4. the sclk input can be high or low at the start and end of each c - bus transaction. 5. the gaps shown between each byte on the cdata and rdata lines in the above diagram are optio nal, the host may insert gaps or concatenate the data as required.
digital pmr (dpmr) baseband processor CMX8341 ? 8.3 function image ? loading the function image ? (fi), which defines the operational capabilities of the device, may be obtained from the cml technical portal, following registration. this is i n the form of a 'c' header file which can be included into the host controller software or programmed into an external serial memory. the maximum possible size of function image tm is 46 kbytes, although a typical fi will be less than this. note that the bo oten pins are only read at power - on or following a c - bus general reset and must remain stable throughout the fi loading process. once the fi load has completed, the booten pins are ignored by the CMX8341 until the next power - up o r c - bus general reset. the booten pins are both fitted with internal low current pull - down devices. for c - bus load operation, both pins should be pulled high by connecting them to dv dd either directly or via a 220k resistor (see figure 16 ). for serial memory load, only booten1 needs to be pulled high in a similar manner, however, if it is required to program the serial memory in - situ from the host, either a ju mper to dv dd or a link to a host i/o pin should be provided to pull booten2 high when required (see figure 17 ). the serial memory interface also controls the vocoder section using a separate chip select (ssout) pin. during boot op erations the ssout will be disabled. once the boot operation has completed, the serial memory chip select (epcsn) will be disabled and the ssout will become operational. once the fi has been loaded, the CMX8341 performs these act ions: (1) the product identification code ($8341) is reported in c - bus register $c5 (2) the fi version code is reported in c - bus register $c9 (3) the two 32 - bit fi checksums are reported in c - bus register pairs $a9, $aa and $b8, $b9 (4) the device wait s for the host to load the 32 - bit device activation code to c - bus register $c8 (5) once activated, the device initialises fully, enters idle mode and becomes ready for use, and the prg flag (bit 0 of the status register) will be set. the checksums should be verified against the published values to ensure that the fi has loaded correctly . once the fi has been activated, the checksum, product identification and version code registers are cleared and these values are no longer available. if an invalid activa tion code is loaded, the device will report the value $dead in register $a9 and must be power cycled before an attempt is made to re - load the fi and re - activate. both the device activation code and the checksum values are available from the cml technical portal. table 7 booten pin states booten2 booten1 c - bus host load 1 1 reserved 1 0 serial memory load 0 1 no fi load 0 0 note: in the rare event that a general reset needs to be issued without the requirement to re - load the fi, the booten pins must both be cleared to '0' before the command is issued. the checksum values will be reported and the device activation code will need to be sent in a similar manner as that shown in figure 17 . there will not be any fi loading delay. this assumes that a valid fi has been previously loaded and that dv dd has been maintained throughout the reset to preserve the data.
digital pmr (dpmr) baseband processor CMX8341 ? 8.3.1 fi loading from host controller the fi can be included into the host controller s oftware build and downloaded into the CMX8341 at power - up over the c - bus interface. the booten pins must be set to the c - bus load configuration, the CMX8341 powered up and placed into program mode, the data can then be sent directly over the c - bus to the CMX8341 . each time the programming register, $c8, is written, it is necessary to wait for the prg flag (irq status register ($c6) b0) to go high before another write to $c8 . th e prg flag going high confirms the write to the programming register has been accepted . the prg flag state can be determined by polling the irq status register or by unmasking the interrupt (interrupt mask register, $ce, b0). the download time is limited b y the clock frequency of the c - bus, with a 5mhz sclk, it should take less than 500ms to complete.
digital pmr (dpmr) baseband processor CMX8341 ? figure 16 fi loading from host booten 2 = 1 booten 1 = 1 power - up or write general reset to device poll $ c 6 until b 0 = 1 ( programming mode entered ) configure prg flag interrupt if required write $ 0001 to $ c 8 write start block 1 address ( db 1 _ ptr ) to $ b 6 write block 1 length ( db 1 _ len ) to $ b 7 wait for prg flag to go high or interrupt write next data word to $ c 8 wait for prg flag to go high or interrupt write start block 2 address ( db 2 _ ptr ) to $ b 6 write block 2 length ( db 2 _ len ) to $ b 7 write $ 0001 to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt write next data word to $ c 8 write start block 3 address ( activate _ ptr ) to $ b 6 write block 3 length ( activate _ len ) to $ b 7 write $ 0001 to $ c 8 wait for prg flag to go high or interrupt send activation code hi to $ c 8 read and verify checksum values in register pair : $ a 9 and $ aa , $ b 8 and $ b 9 send activation code lo to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt booten 1 and booten 2 may be changed from this point on , if required device is now ready for use booten 1 booten 2 v dd
digital pmr (dpmr) baseband processor CMX8341 ? 8.3.2 fi loading from an external serial memor y the fi must be converted into a suitable format for a serial memory programmer (normally intel hex) and loaded into the external serial memory either by the host or an external programmer. the CMX8341 needs to have the booten p ins set to serial memory load and then on power - on, or following a c - bus general reset, the CMX8341 will automatically load the data from the serial memory without intervention from the host controller. figure 17 fi loading from an external serial memory the CMX8341 has been designed to function with either an atmel at25hp512 serial eeprom or the at25f512 serial flash device 1 , however other manufacturers parts may also be suitable. the time taken to load the fi is dependent on the clock frequency: with a 19.2mhz reference clock it should load in less than 1/3 rd second. 1 note that these two devices have slightly different addressing schemes. the CMX8341 is compatible with both schemes. booten 2 = 0 booten 1 = 1 power - up or write general reset to device poll $ c 6 until b 0 = 1 ( fi loaded ) configure prg flag interrupt if required send activation code hi to $ c 8 read and verify checksum values in register pair : $ a 9 and $ aa , $ b 8 and $ b 9 send activation code lo to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt booten 1 and booten 2 may be changed from this point on , if required device is now ready for use booten 1 booten 2 vdd jumper for programming serial memory ( if required )
digital pmr (dpmr) baseband processor CMX8341 ? 8.4 device control the CMX8341 can be set into the relevant mode to suit its environment. these modes are described in the following sections and are programmed over the c - bus: either directly to operational registers or, for parameters that are not likely to change during operat ion, via the programming register ($c8). for basic operation: (1) enable the relevant hardware sections via the power down control register (2) set the appropriate mode registers to the desired state (3) select the required signal routing and gain (4) use the mode control register to place the device into rx or tx mode. to conserve power when the device is not actively processing a signal, place the device into idle mode. this will also command the vocoder section to enter powersaving mode as well. additional powersaving c an be achieved by disabling any unused hardware blocks, however, care must be taken not to disturb any sections that are automatically controlled. note that the bias block must be enabled to allow any of the input or output blocks to function. see: o power down control - $c0 write o modem control - $c1 write o modem configuration - $c7 write . 8.4.1 general notes in normal operation, the most si gnificant registers, in addition to the txdata and rxdata blocks, are: o modem control - $c1 write o irq status - $c6 read o analogue output gain - $b0 writ e o input gain and sign al routing - $b1 write o auxdata/sub - audio write - $c2 write o analogue control - $c3 write setting the mode register to either rx or tx will automatically increase the int ernal clock speed to its operational speed and bring the vocoder section out of its powersave mode, whilst setting the mode register to idle will automatically return the internal clock to a lower (powersaving) speed. to access the program blocks (through the programming register, $c8) the device must be in idle mode. under normal circumstances the CMX8341 manages the main clock control automatically, using the default values loaded in program block 3. 8.4.2 interrupt operation the CMX8341 will issue an interrupt on the irqn line when the irq bit (bit 15) of the irq status register and the irq mask bit (bit 15) are both set to 1. the irq bit is set when the state of the interrupt flag bits in the irq status reg ister change from a 0 to 1 and the corresponding mask bit(s) in the interrupt mask register is(are) set. enabling an interrupt by setting a mask bit (0 ? 1) after the corresponding irq status register bit has already been set to 1 will also cause the irq bit to be set. all interrupt flag bits in the irq status register, except the prg flag (bit 0), are cleared and the interrupt request is cleared following the command/address phase of a c - bus read of the irq status register. the prg flag bit is set to 1 only when it is permissible to write a new word to the programming register. see: o irq status - $c6 read o interrupt mask - $ce write
digital pmr (dpmr) baseband processor CMX8341 ? 8.4.3 signal routing the CMX8341 offers a flexible routi ng architecture, with three signal inputs, a choice of two modulator configurations (to suit 2 - point modulation or i/q schemes) and a single audio output. see: o input gain and sign al routing - $b1 write o modem control - $c1 write o modem configuration - $c7 write the analogue gain/attenuation of each input and output can be set individually. in dpmr mode, the mic and speaker gains are s et by the vocoder section, which is controlled through the analogue control - $c3 write register. in analogue mode, the mic and speaker gains are set by the input gain and output gain registers ($b1 and $b0). see: o analogue output gain - $b0 writ e (tx mod1 and 2) o input gain and sign al routing - $b1 write (rx disc input, tx mod1 and 2) o analogue control - $c3 write (vocoder section mic. and speaker) input 1 should be routed to either of the three input sources (alt, disc or mic), which should be connected as shown in figure 5 and figure 6 . the internal signals output 1 and output 2 are used to provide 2 - point signals and should be routed to the mod1 and mod2 pins, as required. in dpmr mode the microphone and speaker paths are automatically re - routed to the vocoder section, when appropriate. this routing is cont rolled by the data field in the header block, which indicates whether the payload is speech data, and the vocoder section disable bit in the modem control register, $c1. 8.4.4 modem control the CMX8341 operates in one of these operatio nal modes: o idle o rx o tx o pass - through, for direct vocoder access. at power - on or following a reset, the device will automatically enter idle mode, which allows maximum powersaving whilst still retaining the capability of monitoring the auxadc inputs (if enabl ed). it is only possible to write to the programming register whilst in idle mode. by default, the CMX8341 selects digital ( dpmr modem) mode, unless any of the voice, tone or sub - audio bits (b15 - 13) of the modem control register have been set to 1, in which case analogue mode is selected. see: o modem control - $c1 write gpio1 and gpio2 pins (allocated to rxena and txena functions by the fi) reflect bits 0 and 1 of the modem control register, as shown in figure 7 . these can be used to drive external hardware without the host having to intervene. there are two additional gpio pins (gpioa and gpiob) that are programmable under host control .
digital pmr (dpmr) baseband processor CMX8341 ? table 8 modem mo de selection modem control ($c1) b 3 - 0 modem mode gpio2 - txena gpio1 - rxena 0000 idle C low power mode 1 1 0001 rx 1 0 0010 tx 0 1 0011 reserved x x 0100 vocoder section C pass - through 1 1 0101 reserved x x 0110 reserved x x 0111 reserved x x 1xxx reserved x x the pass - through mode is used to control and monitor the vocoder section directly. this cannot be accessed if the CMX8341 is in rx or tx modes. this mode will transfer data to/from the txdata0/rxdata0 register to the vocoder section c - bus register address specified in the programming register ($c8). see section 8.5.12 . the modem control bits are ignored in this mode. table 9 modem control selection 4fsk modem co ntrol ($c1) b7 - 4 rx tx 0000 rx idle tx idle 0001 rx 4fsk formatted tx 4fsk formatted 0010 rx 4fsk raw reserved 0011 rx 4fsk eye tx 4fsk prbs 0100 rx pass - through tx 4fsk preamble 0101 reserved tx 4fsk mod set - up 0110 sync test 0111 reset/abort rese t/abort 1xxx reserved reserved the modem mode bits and the modem control bits should be set together in the same c - bus write. analogue mode is selected by setting any of bits 15 - 13. for digital modem operation, b15 - 13 must be cleared to 0. in tx mode, the CMX8341 operates in dpmr formatted mode. the first block of control channel or payload data should be loaded into the c - bus txdata registers before executing the mode change. a dataready irq will be issued when the registers have been read by the CMX8341 and the host can then supply further blocks of payload data. when all payload data has been transmitted, the CMX8341 will issue a txdone irq and the host can then reset the mode bits to either rx or idle as required. in rx mode, the received signal should be routed through input1 (disc). in dpmr formatted mode, the CMX8341 will fi rst search for frame synchronisation and, when this has been achieved, the following data is demodulated and supplied to the host through the rxdata registers. a dataready irq indicates when each new block becomes available. in dpmr formatted mode, the m odem can detect the end of a call and restart frame sync search automatically. 8.5 dpmr formatted operation the CMX8341 performs all frame building/splitting and fec coding/decoding, which relieves the host controller of a significa nt processing load. during voice calls the CMX8341 can automatically enable and
digital pmr (dpmr) baseband processor CMX8341 ? control the vocoder section, and transfer voice payload data from/to it without host intervention. in rx mode, the CMX8341 monitors address fields in incoming transmissions and only accepts calls if the programmed address requirements are satisfied. this allows the host to remain in a power - down or sleep state until it is really necessary to wake up, extending the battery l ife of the final product design. 8.5.1 tx mode in tx mode operation ($c1, modem control = $0012), the preamble and frame sync are transmitted automatically and data from the txdata block is then formatted and assembled for transmission, until the mode is changed to rx, pass - through or idle . the first block of data should be loaded into the txdata registers before executing the modem mode change to tx. data is transmitted msb (most significant bit) first. the host should write the initial data to the c - bus txdata registers and then set the modem mode to txformat and the mode bits to tx. as soon as the data block has been read from the c - bus txdata registers, the datardy irq will be asserted and the next block of data may be loaded. the call should be terminated by the host sending an end frame to the device. after the last data bit has left the modulator a txdone irq will be issued. at this point it is now safe for the host to change the modem control and modem mode to idle ($c1, modem control = $0000) and turn th e rf transmitter off. if the header frame loaded by the host indicates that a voice call is in progress, the device will automatically enable the vocoder and route encoded voice packets to the modulator in preference to any data provided by the host over c - bus. when the host loads the end frame, the device will automatically disable the vocoder. 8.5.2 tx mode (prbs) in prbs mode tx operation ($c1, modem control = $00 32 ), the preamble and frame sync are transmitted automatically, followed by a prbs pattern conform ing to itu - t o.153 (para 2.1) C giving a 511 - bit repeating sequence. 8.5.3 tx mode test in test mode ($c1 = $0062), simple test waveforms are generated (defined by the dpmr association twg). see section 10.1.20 .
digital pmr (dpmr) baseband processor CMX8341 ? figure 18 tx data flow load data to c - b us txdatablock transaction count = 0 , byte count = 9 set modem control to : txraw , mode = tx irq = datardy ? no gpio 2 and gpio 1 will change to 0 1 and the modem will transmit the preamble , frame sync and data the host should ensure that any external hardware is also set into tx mode ( if not automatically controlled by the gpio pins ). note : yes more data to send ? load data to c - b us txdatablock transaction count ++ , byte count = 9 yes no see rx _ process flow diagram note : set modem control to idle : mode = idle gpio 2 and gpio 1 will change to 11 and the modem will drop into idle mode . the host should ensure that any external hardware is also set into idle mode ( if not automatically controlled by the gpio pins ). note : goto rx _ process goto idle mode ramdac has been enabled data is in 9 byte blocks note : tx _ process irq = txdone ? no yes irq = error , modem status = underflow may occur at this point , if enabled . note : due to internal processing delays in the filters etc , the host should wait for irq = txdone or implement its own delay to ensure all data has been transmitted . note : execute ramdac down execute ramdac up ensure that ramdac speed is fast enough to allow for hardware and internal processing delays note :
digital pmr (dpmr) baseband processor CMX8341 ? 8.5.4 rx mode in rx mode operation ($c1, modem control = $0011), the CMX8341 automatically starts searching for frame synchronisation. when a valid frame sync se quence is detected, an fs1 detect or fs2 detect irq is asserted and the data demodulator is enabled. all following payload data is loaded directly into the c - bus rxdata registers with a dataready irq to indicate when each new block is available. this continues until the end frame is detected or the mode is changed to idle or tx. the host must respond to each dataready irq before the rxdata registers are overwritten by subsequent payload data blocks. if soft data mode has been selected, the payload data is encoded in 4 - bit log - likelihood - ratio format. in this mode the host must be able to service the dataready irqs and rxdata registers at four times the normal rate to avoid overflow. alternatively, additional power saving may be achieved by the ho st monitoring the called irq instead, which will only be asserted when the id match criteria are satisfied. if the recovered header frame indicates that a voice call is in progress, the device will automatically route the payload data to the vocoder in p reference to the host c - bus. 8.5.5 rx mode dpmr in rx dpmr mode operation ($c1, modem control = $0011), the CMX8341 will automatically start searching for frame synchronisation. when a valid frame sync sequence is detected, an fs detect irq is asserted and the data demodulator is enabled. if the burst is then accepted a called irq is asserted and the first message info or cch info block is loaded into the c - bus rxdata registers with a data ready irq. if the control channel fields indicate that the burst is a voice call , received payload data will be sent to the vocoder for decoding. otherwise payload data is loaded into the c - bus rxdata registers with a data ready irq to indicate when each new block is available. if soft data mode has been selected, the payload data is encoded in 4 - bit log - likelihood - ratio format and the host must be able to service the data ready irqs and rxdata registers at four times the normal rate to avoid overflow. 8.5.6 rx mode raw rx mode raw is included to facilitate ber measurement s. in this mode ($c1, modem control = $0021), once a valid f rame s ync has been detected, all following data received is loaded directly into the c - bus rxdata registers. this continues until the end of the burst (even if there is no valid signal at the inp ut). on exiting rx mode raw, there may be a datardy irq pending which should be cleared by the host. note that rx mode raw operation always requires the incoming data to be preceded with a valid preamble and frame sync pattern in order to derive timing inf ormation for the demodulator. the device will update the c - bus rxdata registers with rx payload data as it becomes available. the host must respond to the datardy irq before the rxdata registers are over - written by subsequent data from the modem.
digital pmr (dpmr) baseband processor CMX8341 ? figure 19 rx data flow 8.5.7 rx mode eye in rx 4fsk eye mode ($c1 = $0031) , the filtered received signal is output at the mod1 pin as an eye diagram for test and alignment purposes. a trigger pulse is output at the mod2 pin to allow viewing on a suitable oscilloscope. the trigger pulse is generated directly from the receiver clock source, not from the input signal. rx _ process set modem control to : rxraw , mode = rx irq = datardy ? no gpio 2 and gpio 1 will change to 1 0 , the modem will start to look for frame sync . the host should ensure that any external hardware is also set into rx mode ( if not automatically controlled by the gpio pins ). note : yes more data to receive ? load data from c - b us rxdatablock check transaction count and byte count yes no see tx _ process flow diagram note : set modem control to : rx idle , mode = idle gpio 2 and gpio 1 will change to 11 , and the modem will drop into idle mode . the host should ensure that any external hardware is also set into idle mode ( if not automatically controlled by the gpio pins ). note : goto tx _ process goto idle _ process ramdac has been enabled data is in 9 byte blocks note : if enabled , irq = framesync will occur before irq = datardy note : an irq = datardy may still be pending at this point note :
digital pmr (dpmr) baseband processor CMX8341 ? 8.5.8 rx mode pass - through rx pass - through mode ($c1 = $0041), similar to rx 4fsk eye mode, but without the rrc filter. the typical response is: 300hz - 0.6db 1khz 0db (reference) 2khz - 0.7db 2.5khz - 1.4db 3khz - 2.4db 4khz - 4.9db 6khz - 12.2db 8.5.9 sync mode sync mode ($c1 = $0061), enters continuous afsd synch search mode. used for test/debug only. 8.5.10 reset/abort from each mode, a reset/abort aborts the current state machine and drops into the corresponding (rx or tx) idle mode. the only difference between this and going directly into the corresponding idle mode is that all of the buffers and filters a re flushed out first with reset/abort. in tx mode a number of test and set - up modes are provided to facilitate test and alignment. o prbs (preamble and synchronisation word are automatically transmitted first) o continuous preamble: a repeating sequence of [+ 3 +3 - 3 - 3] symbols o modulation set - up: in two - point mode, a repeating sequence of eight +3 symbols followed by eight - 3 symbols, and in i/q mode a continuous sequence of +3 symbols. 8.5.11 data transfer payload data is transferred from/to the host using blocks of five rx and five tx 16 - bit c - bus registers, allowing up to 72 bits (9 bytes) of data to be transferred in sequence, see table 10 . the lowest 8 bits of the register block are reserved for a byte counter, block id and a transacti on counter. the byte count indicates how many bytes in the data block are valid and avoids the need to perform a full five word c - bus read/write if only a smaller block of data need to be transferred. table 10 c - bus data registers c - bus address function c - bus address function $b5 tx data 0 - 7 and info $b8 rx data 0 - 7 and info $b6 tx data 8 - 23 $b9 rx data 8 - 23 $b7 tx data 24 - 39 $ba rx data 24 - 39 $ca tx data 40 - 55 $bb rx data 40 - 55 $cb tx data 56 - 71 $c5 rx data 56 - 71 bits 7 and 6 hold the transaction counter, which is incremented modulo 4 on every read/write of the data block to allow detection of data underflow and overflow conditions. in tx mode the host must increment the counter on every write to the txdata block and, if the CMX8341 identifies that a block has been written out of sequence, the event bit (c - bus register $c6, b14) will be asserted and an irq raised, if enabled. the device detects that new data from the host is available by the change in the value of the transaction counter, therefore the host should ensure that all the data is available in the txdata block before updating this register (ie, it should be the last register the host writes to in any block transfer). in rx mode, the CMX8341 will automatically increment the counter every time it writes to the rxdata block. if the host
digital pmr (dpmr) baseband processor CMX8341 ? identifies that a block has been written out of sequence, then it is likely that a data overrun condition has occurred and some data has been lost. 8.5.12 vocoder section C pass - through mode to allow the host to communicate directly with the vocoder section for test and configuration purposes, a pass - through mode is available which allows any vocoder section c - bus register to be read or writt en (as appropriate). this mode uses the modem control, txdata0, rxdata0, irq status and program blocks on the CMX8341 . to write to the vocoder section: o set the CMX8341 to 'pass - through' mode (modem control register, $c1=$0004) o wait for the prg flag to be set ($c6 b0) o write the vocoder section data value to the txdata0 register ($b5) o write the vocoder section c - bus address to the programming register ($c8) with b15=0 and b14=1 o wait for the prg flag to be set ($c6 b0). to read from the vocoder section: o set the CMX8341 to 'pass - through' mode (modem control register, $c1=$0004) o wait for the prg flag to be set ($c6 b0) o write the vocoder section c - bus address to the programming register ($c8) with b15=1 and b14=1 o wait for the prg flag to be set ($c6 b0) o read the vocoder section data value from the rxdata0 register ($b8). vocoder section c - bus addresses are all 8 bits long and should be written to bits 0 - 7 of the programming register. bit 15 is the read/write flag (1 = read, 0 = write) and bit 14 is the register - size flag (0 = 16 - bit, 1 = 8 - bit). unused bits should be cleared to zero. when an 8 - bit register is read or written, the data occupies the lower 8 bits of the appropriate data register (txdata0 or rxdata0). 8.5.13 vocoder section C noise gate the vocoder section has an optional, programmable noise gate. this is controlled by the addition of five new 16 - bit c - bus write registers, accessed by pass - through mode (see section 8.5.12 ). once the function image? has been loaded, these new registers will all be set to an initial value of zero. for details of how to configure these registers, see section 10.3 . the purpose of the encoder's noise gate is to remove background noise in between speech pauses. this could be used to remove noise generated in any front - end analogue circuitry, or could be used to help reduce the effects of ambient noi se, perhaps with some degree of user control. three parameters control this noise gate. an upper threshold level controls the point at which the gate opens and allows audio to pass. a lower threshold level controls the point at which the gate closes, there by preventing audio from passing. these two parameters together control the hysteresis and prevent 'chattering'. a third parameter controls how many consecutive frames of audio must be below the lower threshold before the gate closes. this 'gate shut delay ' prevents the tail end of words (like a trailing 's') from being clipped. once the gate shut delay has expired, the gate does not shut abruptly, but closes over a period of 16 frames. each 20ms frame has progressively more attenuation applied, until the f rames are silent. this happens in approximately 6db steps.
digital pmr (dpmr) baseband processor CMX8341 ? the purpose of the decoder's noise gate is to remove audio artefacts after decoding packets of vocoded silence. the noise gate operation is exactly the same as the e ncoder's noise gate, however, only the lower threshold level is programmable. the upper threshold level is fixed to be twice the lower threshold level, and the gate shut delay is fixed to be 10 frames, which is 200ms. 8.5.14 dpmr operating modes and addressing t s 102 490 describes two operating modes for a dpmr radio: o isf C initial services and facilities C out of the box mode o csf C configured services and facilities C managed mode. the CMX8341 can support either of these modes, as selected by b9 of the modem configuration register, $c7 (see user manual section 10.1.25 ). the standard also defines two addressing schemes: 24 - bit binary or 7 - digit bcd (binary - coded - decimal). radios operating in isf mode are required to use binary addressing, but in csf mode either binary or bcd addressing can be used. both addressing schemes are supported by the CMX8341 , selected by b11 in the modem configuration register, $c7 (see u ser manual section 10.1.25 ). the host can load two own ids (binary or bcd) into program block 1 for use in both tx and rx modes. in tx mode the host can select which of these to send in the caller id field of the outgoing call. in rx mode, the CMX8341 compares the called id field from incoming calls against each of its own ids, and will accept the call if a valid id match is found. address matching can be disabled using b12 of the m odem configuration register, $c7, in which case the CMX8341 will accept all incoming calls. the CMX8341 implements bcd address translation in both tx and rx, to relieve the host of the p rocessing required to map bcd digits to over - air binary values. bcd addresses can include wildcard digits in any of the lower four digits, and there are ten bcd all - call addresses with wildcards in all six lower digits. the CMX8341 handles wildcard digits appropriately during address matching in rx. binary addresses do not support group calling with wildcards, but the CMX8341 provides six binary - only group call ids in addition to the two own ids. thes e can be programmed by the host to be used for address matching in rx only. ts 102 490 also specifies a system - wide all call facility using the communication format field in the header frame (ts 102 490 section 5.8). the normal setting for this field is peer - to - peer, but when set to call all the CMX8341 will always accept the call regardless of isf/csf mode and all other address settings. the host should take care not to transmit in all call mode unless actua lly intended. 8.5.15 isf addressing the services available in isf mode are described in ts 102 490 section 8.1. radios using isf mode provide a style of operation broadly similar to analogue pmr446. noise gate output upper threshold level lower threshold level gate shut delay original signal voice background noise progressive attenuation
digital pmr (dpmr) baseband processor CMX8341 ? isf mode requires 24 - bit binary addressing to be used, with only the top 8 bits (the common id field) in active use for addressing isf mode devices. the remaining 16 bits must be set to all 1s. this is the default mode of the CMX8341 and the default common ids are: o id1: $01 o id 2: $02. the isf common all - call id is $ff. when in isf mode the CMX8341 will always accept calls to this address regardless of other address settings. 8.5.16 csf addressing the services available in csf mode are describe d in ts 102 490 section 8.2 and annex a. csf mode does not mandate bcd addressing unless the host implements the standard user interface, but the advantages of bcd addressing are direct mapping of user keypad entries to destination addresses and the option of wildcard digits to implement group calls. the host can select the addressing mode using b11 of the modem configuration register, $c7. 8.5.17 tx mode ( dpmr formatted) in tx dpmr formatted mode ($c1, modem control = $0012), the CMX8341 builds header, control channel and end information blocks, performs all fec coding, interleaving and scrambling functions and inserts frame sync and colour code sequences to generate the required frame formats for transmission. during voi ce calls the CMX8341 can automatically enable and control the vocoder section and transfer voice payload data from/to it without host intervention. the txdata registers are used to transfer header and end information fields in ad dition to payload data. the block id field in the txdata0 register informs the CMX8341 how to process each transfer. b5 - 4 block id 00 hdr - header data 01 pld - payload data 10 pls - payload data with slow dat a 11 end - end data the host should preload the txdata registers with header data before placing the device in tx dpmr formatted mode. the CMX8341 reads the header type field to determine the burst type and th en sends the preamble and header frame. if the call information field indicates that repeated extended wake - up headers are to be sent, the CMX8341 will do so automatically. the header fields are saved for re - u se when building the control channel information blocks in following payload frames: the host does not need to re - load them. header data: txdata rxdata 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 le 0 own id header type counter 0 0 1 0 0 1 1 0 0 call informa tion comms mode 2 version format 0 0 0 0 0 0 colour code 3 0 0 0 0 binary mode: address C C C C
digital pmr (dpmr) baseband processor CMX8341 ? header type: see ts 102 490 section 5.11 (communication start, ack, etc.) own id: 00 = tx: reserved rx: all call received 01 = tx: send own id 1 (from program block 1) rx: own id1 matched 10 = tx: send own id 2 (from program block 1) rx: own id2 matched 11 = reserved reserved : see ts 102 490 section 5.4 (00) comms mode: see ts 102 490 section 5.7 (sets data type and source, host or vocoder) le: late - entry (rx only) C some data fields may be missing due to late entry into the call call i nformation: see ts 102 490 section 5.10 (includes extended headers, data frame size etc.) comms format: see ts 102 490 section 5.8 (all - call or peer - to - peer) 00 = call all (broadcast) 01 = peer - to - peer communication 10 = reserved 11 = reserved version: see ts 102 490 section 5.16 (vocoder version) note: the dpmr association has agreed standard bit allocations for the voice burst and the host should set this field accordingly. 00 = dvsi ambe+2 01 = to be selected by chinese dra 10 = ralcwi 11 = manufacturer defined colour code: 6 - bit index into the colour code table as shown in ts 102 490 section 6.1.5 address: tx: destination (called) address. rx: originating (caller) address. payload data: see table 10 and user man ual section 10.1.12 payload data with slow data: see table 10 and user manual section 10.1. 12
digital pmr (dpmr) baseband processor CMX8341 ? end data: txdata rxdata 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 tx wait ack req end type counter 1 1 0 0 1 1 1 0 0 0 0 0 0 reserved 0 status message 2 not used 3 not used 4 not used end type: see ts 102 490 section 5.12 ack request: see ts 102 490 section 5.13 tx wait: see ts 102 490 section 5.14 status msg: see ts 102 490 section 5.15 reserved : 0000 depending on the burst type, the CMX8341 will expect the host to load a series of payload data blocks and/or an end data block (except f or ack bursts which consist of a bare header frame). disconnect bursts contain a repeated header/end frame pair but the host should only load single blocks of header and end data fields, as the CMX8341 will send t he duplicate frames automatically. if the vocoder section is enabled and the communication mode field in the header frame indicates a voice call, the CMX8341 will automatically enable the vocoder section microph one input and route payload data from the vocoder section for transmission. note that the vocoder section takes a finite time to encode the incoming voice data, during which the CMX8341 will automatically insert silence data into the payload frames. the host can load an end frame at any point during the call. to terminate the voice call, the host should place the CMX8341 modem into tx idle mode ($c1, modem control = $000 2). the CMX8341 will disable the vocoder section and send the end frame that was loaded previously. at the end of all dpmr transmissions the CMX8341 will issue a txdone i rq when it is safe for the host to place the device back into idle mode ($c1, modem control = $0000). 8.5.18 rx mode ( dpmr formatted) in rx dpmr mode ($c1, modem control = $0011), the CMX8341 automatically splits incomin g calls to extract header information, control channel information and end information blocks and performs all the necessary de - scrambling, de - interleaving and fec decoding functions. in speech calls, the CMX8341 can automatically enable the vocoder section when required and transfer received speech data without host intervention. the rxdata registers are used to transfer header and end data fields in addition to payload data. the block id field in the rxdata0 regi ster informs the host what type of data block each transfer contains. the field layout in the rxdata registers for the different transfer types is the same as for tx dpmr formatted mode (section 8.5.17 ). when pl aced in rx dpmr formatted mode, the CMX8341 automatically starts searching for the dpmr frame sync sequences. in addition to detecting the 48 - bit fs1 frame sync at the start of a transmission, the CMX8341 can also perform late entry into a call by detecting two successive copies of the 24 - bit fs2 sequence at the correct two - frame spacing. when a valid frame sync sequence has been detected, an fs1 detect or fs2 detect irq is issued and the data demodulator is enabled. the CMX8341 then decodes the contents of the header frame (after an fs1 detect) or the following four control channel information blocks (after an fs2 detect). t he header information or control channel information crcs are checked and processing continues only if a full set of valid fields has been received. header frames contain two duplicate header information blocks: the CMX8341 checks both block crcs, uses the first valid block and discards the other.
digital pmr (dpmr) baseband processor CMX8341 ? when repeated extended wake - up header frames are received (see ts 102 490 section 11.1), the CMX8341 will decode the first va lid header but delay address checking until all following repeat headers have been received. this maximises the time the host can be kept in powersave. address checking now takes place depending on isf/csf mode and the addressing mode selected. the commun ications format field is checked first: if this is set to call all the call is accepted. if not, the called station id is checked against the devices own ids (programmed by the host into program block 1) and if a match is found the call is accepted. in isf mode, the common all - call id $ff is also always accepted. in any of these cases a called irq is issued to the host, otherwise the call is dropped with no further host notification and the CMX8341 returns to frame sync search. address matching can be disabled by setting b12 of the modem configuration register, in which case the CMX8341 will accept all incoming calls. the header fields are presented to the host in t he rxdata block. late entry is indicated by bit 15 of rxdata0: in this case the header type and call information fields in the header data block returned to the host will not contain valid data, as these fields are only sent in header frames and are no t re - sent in the control channel information blocks during a call. depending on the burst type, the CMX8341 will decode the following payload and/or end frames and present their contents to the host or vocoder. if the vocoder section is enabled and the communication mode field in the header frame indicates a voice call, the CMX8341 will automatically enable the vocoder section speaker output and route payload data to the vocoder section for decoding. in this mode, the data is transferred in 4 - bit log - likelihood - ratio format. otherwise, payload data is presented to the host in the rxdata registers in soft or hard format, as specified. when an end frame is received, the CMX8341 will report its contents to the host, disable the vocoder (if necessary) and return to frame sync search. all frame sync sequences, colour codes and crcs contained in payload superframes are checked and an e vent irq is issued when any are received incorrectly. if all the frame sync sequences, colour codes and crcs in a superframe are received incorrectly, the superframe is considered corrupt. the host can set a threshold for consecutive corrupt superframes ( in program block 0), after which the CMX8341 will issue an event irq, drop the call and return to frame sync search. see: o rxdata 0 - $b8 read o auxdata/sub - audio read - $cc read . 8.5.19 slow data slow data may be transferred in voice calls alongside voice payload data, by setting the block id to payload with slow data and using the auxdata registers. if the vocoder section is enabled, th ere will be no voice payload transfers and so dummy payload transfers are used with the byte counter field cleared to zero. in type1 and type 2 data calls, the slow data field is used to control the data flow over - air and so is generated or decoded by the CMX8341 itself and the only data field that is visible to the host is the format field as defined in ts 102 490 section 5.9.2. which is made available, or supplied by the host, in the lowest 4 bits of the auxdata register. in t x mode: o load auxdata register with two bytes of slow data: auxdata/sub - audio write - $c2 write o set communications mode to voice with slow data o set blockid to payload with slow data: txdata 0 - $b5 write o set byte counter field (to zero if vocoder section is in use): txdata 0 - $b5 write . the CMX8341 has an internal 64 - byte buffer for slow data. while the host keeps this internal data buffer topped - up the CMX8341 will continue to transmit slow data and add the continuation bits to the over - air data. note that only two bytes of slow data are sent over - air for every 36 bytes of voice payload, so the buffer may overflow if a large quantity of slow data is loaded continuously. the host is expected to track the number of bytes in the buffer. bit 10 of the status register $c6 is set to 1 and an interrupt raised, if unmasked, when there are only two bytes left in the fifo. when th e host allows the internal buffer to empty, the CMX8341 will terminate the
digital pmr (dpmr) baseband processor CMX8341 ? transmission of slow data in the current burst. it is not possible to re - start slow data transmission within a burst. in rx mode: o blockid will report pay load with slow data: rxdata 0 - $b8 read o communications mode will report voice with slow data o if payload is being sent to the vocoder section, then the byte counter field will be cleared to zero o slow data is available in the au xdata register: auxdata/sub - audio read - $cc read when the slow data transfer has completed, the CMX8341 will stop presenting data to the host. 8.6 analogue mode 8.6.1 tx mode analogue in analogue pmr mode, the m ic input is processed and summed with either the external sub - audio signal on the alt input or the internally generated sub - audio signal and then presented at the mod1 and mod2 pins. the choice is determined by program block p2.0 b5 (see section 10.2.3 ). 8.6.2 rx mode analogue in analogue pmr mode the received signal should be routed through input1 (disc). the signal is filtered and processed so that the inband signal is output on the audio pin and the sub - audio signal is either out put on the auxdac4 pin or routed to the internal sub - audio detector. the choice is determined by program block p2.0 b4 (see section 10.2.3 ). 8.7 squelch operation many limiter/discriminator chips provide a noise - quieting squelch c ircuit around an op - amp configured as a filter. this signal is conventionally passed to a comparator to provide a digital squelch signal, which can be routed directly to one of the CMX8341 s gpio pins or to the ho st. however with the CMX8341 , the comparator and threshold operations can be replaced by one of the auxadcs with programmable thresholds and hysteresis functions. see: o irq status - $c6 read o modem configuration - $c7 write 8.8 gpio pin operation the CMX8341 provides four gpio pins. rxena (gpio1) and txena (gpio2) are configured to reflect the tx/rx state of the mode register (txena and rxena, active low). see: o modem configuration - $c7 write . note that rxena and txena will not change state until the relevant mode change has been executed by the CMX8341 . this is to allow the host sufficient time to load the relevant data buffers and the CMX8341 time to encode the data required prior to its transmission. there is thus a fixed time delay be tween the gpio pins changing state and the data signal appearing at the mod output pins. during the power - on sequence (until the fi has completed its load sequence) these pins have only a weak pull - up applied to them, so care should be taken to ensure that any loading during this period does not adversely affect the operation of the unit. gpio a and b are host programmable for input or output using the auxadc configuration register, $a7. the default state is input, with a weak pull - up. when set for input, t he values can be read back using the modem status register, $c9.
digital pmr (dpmr) baseband processor CMX8341 ? 8.9 auxiliary adc operation the inputs to the two auxiliary adcs can be independently routed from any of the signal input pins under control of the auxadc configuration register, $a7. conversions will be performed as long as a valid input source is selected. to stop the adcs, the input source should be set to off. register $c0, b6, bias, must be enabled for auxiliary adc operation. averaging can be applied to the adc readings by selecting the re levant bits in the auxadc configuration register, $a7. the length of the averaging is determined by the value in p3.0 and p3.1 and defaults to a value of 0. this is a rolling average system such that a proportion of the current data will be added to the la st average value. the proportion is determined by the value of the average counter in p3.0 and p3.1. for an average value of: 0 = 50% of the current value will be added to 50% of the last average value 1 = 25% of the current value will be added to 75% of t he last average value 2 = 12.5% etc. the maximum useful value of this field is 9. high and low thresholds may be independently applied to both adc channels (the comparison is applied after averaging, if this is enabled) and an irq generated when a rising e dge passes the high threshold or a falling edge passes the low threshold, see figure 20 . the thresholds are programmed via the auxadc threshold register, $cd. figure 20 auxad c irq operation auxiliary adc data is read back in the auxadc data registers ($a9 and $aa) and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). see: o auxadc configuration - $a7 write o auxadc1 data and status - $a9 read o auxadc2 data and status - $aa read o auxadc threshold data - $cd write . 8.10 auxiliary dac/ramdac operation the four auxiliar y dac channels are programmed via the auxdac data/control register, $a8. auxdac channel 1 may also be programmed to operate as a ramdac, which will automatically output a pre - programmed profile at a programmed rate. the auxdac data/control register, $a8, w ith b12 set, controls this mode of operation. the default profile is a raised cosine (see table 15 ), but this may be over - written signal irq irq irq irq high threshold low threshold
digital pmr (dpmr) baseband processor CMX8341 ? with a user - defined profile by writing to p3.11. the ramdac operation is only available in tx mode a nd, to avoid glitches in the ramp profile, it is important not to change to idle or rx mode whilst the ramdac is still ramping. the auxdac outputs hold the user - programmed level during a powersave operation if left enabled, otherwise they will return to ze ro. note that access to all four auxdacs is controlled by the auxdac data/control register, $a8, and therefore to update all auxdacs requires four writes to this register. it is not possible to simultaneously update all four auxdacs. auxdac4 is used in an alogue mode to output the filtered sub - audio signal. see: o auxdac data / control - $a8 writ e . 8.11 digital system clock generators figure 21 digital clock generation schemes the CMX8341 requires a 19.2mhz reference clock source. ref clk div / 1 to 512 $ ac b 0 - 8 pd vco pll div / 1 to 1024 $ ab b 0 - 9 lpf sysclk 1 ref sysclk 1 div vco op div / 1 to 64 $ ab b 10 - 15 sysclk 1 pre - clk $ ac b 11 - 15 sysclk 1 output 384 khz - 20 mhz 48 - 192 khz ( 96 khz typ ) sysclk 1 vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) ref clk div / 1 to 512 $ ae b 0 - 8 pd vco pll div / 1 to 1024 $ ad b 0 - 9 lpf sysclk 2 ref sysclk 2 div vco op div / 1 to 64 $ ad b 10 - 15 sysclk 2 pre - clk $ ae b 11 - 15 sysclk 2 output 384 khz - 20 mhz 48 - 192 khz ( 96 khz typ ) sysclk 2 vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) ref clk div / 1 to 512 p 3 . 4 pd vco pll div / 1 to 1024 p 3 . 5 lpf mainclk ref mainclk div vco op div / 1 to 64 p 3 . 3 & 3 . 6 mainclk pre - clk mainclk output 384 khz - 50 mhz ( 24 . 576 mhz typ ) 48 - 192 khz ( 96 khz typ ) mainclk vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) to internal adc / dac dividers auxadc div p 3 . 3 & p 3 . 6 aux _ adc ( 83 . 3 khz typ ) osc 19 . 2 mhz reference clock
digital pmr (dpmr) baseband processor CMX8341 ? 8.11.1 main clock operation a digital pll is used to create the main clock (nominally 24.576mhz) for the internal sections of the CMX8341 . at the same time, other internal clocks are generated by division of either the reference clock or the main clock pre - clock. these internal clocks are used for determining the sample rates and conversion times of a - to - d and d - to - a converters, running a genera l purpose (gp) timer and the signal processing block. in particular, it should be noted that in idle mode the setting of the gp timer divider directly affects the c - bus latency (with the default values this is nominally 250 s). the CMX8341 defaults to the settings appropriate for a 19.2mhz oscillator, as given in p3.2 to p3.7. see: o program block 3 C auxdac, ramdac and clock control . 8.11.2 system clock operation two system clock outputs, sysclk1 and sysclk2, are available to drive additional circuits, as required. these are digital phase locked loop (pll) clocks that can be programmed via the system clock registers with suitable values chosen by the user. the system clock pll con figure registers ($ab and $ad) control the values of the vco output divider and main divide registers, while the system clock ref. configure registers ($ac and $ae) control the values of the reference divider and signal routing configurations. the plls are designed for a reference frequency of 96khz. if not required, these clocks can be independently powersaved. the clock generation scheme is shown in the block diagram of figure 21 . note that at power - on, these pins are disabled. se e: o sysclk 1 and sysclk 2 pll data - $ab, $ad write o sysclk 1 and sysclk 2 ref - $ac and $ae write . 8.12 signal level optimisation the internal signal processing of the CMX8341 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits. for a device working from a 3.3v 10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) - (2 x 0.3v)] volts pk - pk = 838mv rms, assuming a sine wave signal. this should not be exceeded at any stage. in analogue mode, an input agc function is provide to optimise the mic input level across a wid e dynamic range. in this mode the effects of pre - emphasis and de - emphasis as well as overload conditions should be taken into account when determining appropriate input levels. 8.12.1 transmit path levels for the maximum signal out of the mod1 and mod2 attenuator s, the signal level at the output of the modem block is set to be 0db, the fine output adjustment ($c8 p4.2 - 4.3) has a maximum attenuation of 3.5db and no gain, whereas the coarse output adjustment ($b0: b14 - 12, b10 - 8) has a variable attenuation of up to 1 2db in 2db steps and a mute setting (>40db), and no gain.
digital pmr (dpmr) baseband processor CMX8341 ? figure 22 tx level adjustments (analogue) figure 23 tx levels (digital) 8.12.2 receive path levels the coarse input adjustment ($b1) has a variable gain of up to +22.4db and no attenuation. with the lowest gain setting (0db), the maximum allowable input signal level at the discfb pin would be 838mv rms. this signal level is an absolute maximum, which should not be exceeded. audio tones sub - audio processing voice processing mux $ b 1 : b 5 - 2 mux $ c 1 : b 15 - 12 audio mod 1 mod 2 disc alt mic input 1 input 2 output 1 output 2 fine gain : $ cd : 1 xxx fine gain : $ cd : 1 xxx coarse gain : $ b 0 : b 14 - 12 coarse gain : $ b 0 : b 10 - 8 coarse gain : $ b 0 : b 3 - 0 audio tone tx level : $ c 3 : 6 xxx sa tx level : $ cd : 4 xxx input 2 gain : $ b 1 : b 15 - 13 input 1 gain : $ b 1 : b 12 - 10 voice tx level $ c 3 : 2 xxx mux p 2 . 1 : b 6 sum mux p 2 . 1 : b 5 vocoder input gain : $ b 0 : b 6 - 4 mux $ b 1 : b 9 - 6 dpmr formatter mux $ b 1 : b 9 - 6 audio mod 1 mod 2 disc alt mic input 1 input 2 output 1 output 2 fine gain : $ cd : 1 xxx fine gain : $ cd : 1 xxx coarse gain : $ b 0 : b 14 - 12 coarse gain : $ b 0 : b 10 - 8 coarse gain : $ b 0 : b 3 - 0 input 2 gain : $ b 1 : b 15 - 13 input 1 gain : $ b 1 : b 12 - 10 mux p 2 . 1 : b 6 mux p 2 . 1 : b 5 vocoder input gain : $ b 0 : b 6 - 4 ralcwi vocoder encode fec 4 fsk modulator vocoder input secondary gain : $ c 3 : b 7 - 4 mux $ b 1 : b 5 - 2
digital pmr (dpmr) baseband processor CMX8341 ? figure 24 rx level adjustments (analogue) figure 25 rx level adjustments (digital) 8.13 tx spectrum plots the followin g figure shows the tx spectrum when using a suitable signal generator as measured on a spectrum analyser using the CMX8341 internal prbs generator. audio tones sub - audio processing voice processing mux $ b 1 : b 5 - 2 mux $ c 1 : b 15 - 12 mux $ b 1 : b 9 - 6 audio mod 1 mod 2 disc alt mic input 1 input 2 fine gain : $ cd : 1 xxx fine gain : $ cd : 1 xxx coarse gain $ b 0 : b 14 - 12 coarse gain : $ b 0 : b 10 - 8 coarse gain : $ b 0 : b 3 - 0 audio tone rx level : $ c 3 : 7 xxx sa rx level : $ cd : 5 xxx input 2 gain : $ b 1 : b 15 - 13 input 1 gain : $ b 1 : b 12 - 10 voice rx gain $ c 3 : 3 xxx dac 4 vocoder input gain : $ b 0 : b 6 - 4 4 fsk demodulator mux $ b 1 : b 5 - 2 mux $ b 1 : b 9 - 6 audio mod 1 mod 2 disc alt mic input 1 input 2 fine gain : $ cd : 1 xxx fine gain : $ cd : 1 xxx coarse gain $ b 0 : b 14 - 12 coarse gain : $ b 0 : b 10 - 8 coarse gain : $ b 0 : b 3 - 0 audio tone rx level : $ c 3 : 7 xxx input 2 gain : $ b 1 : b 15 - 13 input 1 gain : $ b 1 : b 12 - 10 vocoder speaker gain $ c 3 : b 3 - 0 outp vocoder input gain : $ b 0 : b 6 - 4 dpmr de - format fec decode ralcwi vocoder
digital pmr (dpmr) baseband processor CMX8341 ? figure 26 tx modulation sp ectra - 4800bps r e f l v l - 1 8 d b m r e f l v l - 1 8 d b m r b w 5 0 0 h z v b w 2 k h z s w t 7 0 0 m s r f a t t 1 0 d b a u n i t d b m 3 . 5 k h z / c e n t e r 4 4 6 . 1 m h z s p a n 3 5 k h z 1 v i e w 1 s a - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 1 1 8 - 1 8 1 m a r k e r 1 [ t 1 ] - 7 5 . 8 5 d b m 4 4 6 . 0 9 6 3 1 2 5 0 m h z 1 [ t 1 ] - 7 5 . 8 5 d b m 4 4 6 . 0 9 6 3 1 2 5 0 m h z c h p w r - 2 1 . 1 9 d b m a c p u p - 6 6 . 2 5 d b a c p l o w - 6 7 . 4 2 d b a l t 1 u p - 8 3 . 6 3 d b a l t 1 l o w - 8 4 . 5 8 d b c l 2 c l 2 c l 1 c l 1 c 0 c 0 c u 1 c u 1 c u 2 c u 2 d a t e : 1 3 : 4 5 : 4 4
digital pmr (dpmr) baseband processor CMX8341 ? 8.14 c - bus register summary table 11 c - bus registers addr. (hex) register word size (bits) $01 w c - bus reset 0 $a7 w auxadc configuration 16 $a8 w auxdac data and control 16 $a9 r auxadc1 data and status/che cksum 2 hi 16 $aa r auxadc2 data and status/checksum 2 lo 16 $ab w sysclk 1 pll data 16 $ac w sysclk 1 ref 16 $ad w sysclk 2 pll data 16 $ae w sysclk 2 ref 16 $af reserved $b0 w analogue output gain 16 $b1 w input gain and signal routing 16 $b2 reserved $b3 reserved $b4 reserved $b5 w txdata 0 16 $b6 w txdata 1 16 $b7 w txdata 2 16 $b8 r rxdata 0/checksum 1 hi 16 $b9 r rxdata 1/checksum 1 lo 16 $ba r rxdata 2 16 $bb r rxdata 3 16 $bc reserved $bd reserved $be reserve d $bf reserved $c0 w power down control 16 $c1 w modem control 16 $c2 w auxdata/sub - audio write 16 $c3 w vocoder section analogue gain 16 $c4 reserved $c5 r rx data 4 16 $c6 r irq status 16 $c7 w modem configuration 16 $c8 w programming register 16 $c9 r modem status 16 $ca w tx data 3 16 $cb w tx data 4 16 $cc r auxdata/sub - audio read 16 $cd w auxadc threshold data 16 $ce w interrupt mask 16 $cf reserved all other c - bus addresses (including those not listed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation.
digital pmr (dpmr) baseband processor CMX8341 ? 9 performance specification 9.1 electrical performance 9.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (av dd - av ss , dv dd - dv ss ) - 0.3 4.0 v supply (dv core - dv ss ) - 0.3 2.16 v voltage on any pin to v ss - 0.3 v dd + 0.3 v current into or out of any v dd or v ss pins - 120 +120 ma current into or out of any other pin - 20 +20 ma l8 package min. max. units total allowable power dissipation at tamb = 25oc 2190 mw ... derating 21.9 mw/oc storage temperature - 55 +125 oc operating temperature - 40 +85 oc 9.1.2 operating limits correct operation of the device ou tside these limits is not implied. notes min. max. units supply (av dd - av ss , dv dd - dv ss ) 3.0 3.6 v supply (dv core - dv ss ) 1.7 1.9 v operating temperature - 40 +85 oc xtal/external clock frequency 1 3.0 24.576 mhz note: 1. correct opera tion of the device requires the following specific frequencies to be applied: a reference clock to xtal/clk (pin 55) = 19.2mhz 100ppm
digital pmr (dpmr) baseband processor CMX8341 ? 9.1.3 operating characteristics details in this section represent design target values and are not currently guaranteed. f or the following conditions unless otherwise specified: external components as recommended in figure 2 and table 2 . reference clock frequency = 19.2mhz ? 0.01% (100ppm); tam b = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v; dv core = 1.7v to 1.9v; v dec = 2.5v; v bias = av dd /2. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in b it rate bandwidth. input stage gain = 0db. output stage attenuation = 0db. maximum load on digital outputs = 30pf. current consumption figures quoted in this section apply to the device when loaded with 8341 fi - 1.x only. the use of other function images ca n modify the current consumption of the device. dc parameters notes min. typ. max. units supply current 11 all powersaved di core C C dd C dd C idle mode 12 di core C C dd C C dd 13 C C rx mode (excluding vocoder section) 12 di dd (4800bps C C C dd (9600bps C C C dd (4800bps C C C dd (9600bps C C C dd (av dd = 3.3v) C C tx mode (excluding vocoder section) 12 di dd (4800bps C C C dd (9600bps C C C dd (4800bps C C C dd (9600bps C C C dd (av dd = 3.3v) C C vocoder section di core C C dd C C dd (av dd = 3.3v) 14 C C additional current for each auxiliary system clock (output running at 4mhz) di dd (dv dd = 3.3v, v dec = 2.5v) C C additional current for each auxiliary adc di dd ( dv dd = 3.3v, v dec = 2.5v) C C additional current for each auxiliary dac ai dd (av dd = 3.3v) C C notes: 11 tamb=25c: not including any current drawn from the device pins by external circuitry. 12 system clocks: auxiliary circuits disabled, but all other digital circuits (including the main clock pll) enabled. 13 may be further reduced by power - saving unused sections. 14 adc or dac enabled in vocoder section.
digital pmr (dpmr) baseband processor CMX8341 ? dc parameters (continued) notes min. typ. max. unit re ference clock input input logic 1 70% C C dv dd input logic 0 C C 30% dv dd input current (vin = dv dd ) C C 40 a input current (vin = dv ss ) ? 40 C C a c - bus interface and logic inputs input logic 1 80 % C C dv dd input logic 0 C C 20 % dv dd input leakage current (logic 1 or 0) ? 5 .0 C 5 .0 a input capacitance C C 7.5 pf c - bus interface and logic outputs output logic 1 (i oh = 2ma) 90% C C dv dd output logic 0 (i ol = - 5ma) C C 10% dv dd off state leakag e current C C 10 a irqn (vout = dv dd ) ? 5 .0 C + 5 .0 a reply_data (output hiz) ? 5 .0 C + 5 .0 a v bias 21 output voltage offset wrt av dd /2 (i ol < 1 ? a) C 2% C av dd output impedance C 22 C k ? notes: 21 applies wh en utilising v bias to provide a reference voltage to other parts of the system. when using v bias as a reference, v bias must be buffered. v bias must always be decoupled with a capacitor as shown in figure 2 and table 2 .
digital pmr (dpmr) baseband processor CMX8341 ? a c parameters notes min. typ. max. unit reference clock input 'high' pulse width 15 C C C C C C ? C C C C ? C C C C system clk 1/2 outputs ref. clock input to clock_out timing: (in high to out high) 32 C C C C v bias start - up time (from powersave) C C microphone, alternative and discriminator inputs (mic, alt, disc) input impedance 34 C C ? C C dd load resistance (feedback pins) 80 C C ? ? ? C C C C programmable input gain stage 36 gain (at 0db) 37 ? ? ? ? notes: 31 characterised and specified at 6.144mhz only. 32 characteristics when driving the reference clock input with an external clock source. 33 6.144mhz reference clock selected (scale for 19.2mhz). 34 with no external components connected, measured at dc. 35 centred about av dd /2; after multiplying by the gain of input circuit (with external components connected ). 36 gain applied to signal at output of buffer amplifier: discfb, altfb or micfb 37 design value. overall attenuation input to output has a tolerance of 0db 1.0db
digital pmr (dpmr) baseband processor CMX8341 ? a c parameters notes min. typ. max. unit modulator outputs 1/2 and audi o output (mod1, mod2, audio) power - up to output stable 41 C modulator attenuators attenuation (at 0db) 43 ? ? ? ? ? C C ? ? C C ? dd = 3.3v) C C C dd C C C ? audio attenuator attenuation (at 0db) 43 ? ? ? ? ? C C ? ? C C ? dd = 3.3v) C C C dd C C C ? notes: 41 powe r - up refers to issuing a c - bus command to turn on an output. these limits apply only if v bias is on and stable. at power supply switch - on, the default state is for all blocks, except the reference clock and c - bus interface, to be in placed in powersave m ode. 42 small signal impedance, at av dd = 3.3v and tamb = 25c. 43 with respect to the signal at the feedback pin of the selected input port. 44 centred about av dd /2; with respect to the output driving a 20k ? dd /2.
digital pmr (dpmr) baseband processor CMX8341 ? a c parameters (cont.) notes min. typ. max. unit auxiliary signal inputs (aux adc 1 to 4) source output impedance 51 C C ? auxiliary 10 bit adcs resolution C C C C dd conversion time 52 C C C C ? C C C C C C C auxiliary 10 bit dacs resolution C C C C dd offset error 55, 56 0 C C C ? C C C C notes: 51 denotes output impedance of the driver of the auxiliary input signal, to ensure < 1 bit additional error under nominal conditions. 52 with an auxiliary clock frequency of 6.144mhz. 53 guaranteed monotonic with no missing codes. 54 centred about av dd /2. 55 specified between 2. 5% and 97.5% of the full - scale range. 56 calculated from the line of best fit of all the measured codes. 57 measured at dc.
digital pmr (dpmr) baseband processor CMX8341 ? a c parameters (cont.) notes min. typ. max. unit vocoder section performance sample rate C C C C C C C C C C C C C C C C ? C C dd adc sinad 69, 70 C C C C notes: 69 internal gain settings are 0db on input gain for the opti mum vocoded level and +6db on output gain for the optimum vocoded level, subject to further characterisation. 70 the internal adc is a sigma - delta type which samples at 2.4mhz. it is important that there is no significant energy close to this frequency o r at any of its harmonics, thus avoiding the need for an external low - pass anti - alias filter. 71 the internal dac is a sigma - delta type which samples at 2.4mhz. it will output energy at this frequency and its harmonics. should this present a problem, it is suggested that some external filtering be used at the audio outputs. 72 excludes the 20/40/60/80 ms sample collection period. 73 measured whilst driving a 600 ? ss.
digital pmr (dpmr) baseband processor CMX8341 ? 9.1.4 parametric performance details in this section represent design target values and are not currently guaranteed. for the following conditions unless otherwise specified: external components as recommended in figure 2 and table 2 . reference clock frequency = 19.2mhz ? 0.01% (100ppm); tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v; dv core = 1.7v to 1.9v; v dec = 2.5v; v bias = av dd /2. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltag e, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db. output stage attenuation = 0db. maximum load on digital outputs = 30pf. all figures quoted in this section apply to the device when loaded with 8341 fi - 1.x only. the use of other function images, can modify the parametric performance of the device. dpmr modem notes min. typ. max. unit modem symbol rate 2400 C C C C C C C C C C C C C C dd - 0.5 v notes: 75 transmitting continuous default preamble. 76 see data sheet section 8.13 . 77 measured at baseband C audio performance notes min. typ. max. unit audio compandor attack time C C C C C C C C inband tone encoder frequency range 288 C C C ? C analogue channel audio filtering pass - band (nominal bandwidth): 12.5khz channel 83 300 C C
digital pmr (dpmr) baseband processor CMX8341 ? audio performance notes min. typ. max. unit pass - band gain (at 1.0 khz ) C 0 C db pass - band ripple (wrt gain at 1.0 khz ) ? 2.0 0 +0.5 db stop - band attenuation 33.0 C C db residual hum a nd noise tx 84 C ? 47 C dbm residual hum and noise rx 84 C ? 74 C dbm pre - emphasis 83 C +6 C db/oct de - emphasis 83 C ? 6 C db/oct audio scrambler inversion frequency C 3300 C hz pass - band 320 C 2900 hz audio expandor input signal range 85 C C 0.55 vrms notes: 80 measured at mod 1 or mod 2 output. 81 av dd = 3.3v and tx audio level set to 871mv p - p (308mvrms). 82 av dd = 3.3v. 83 see figure 12 and figure 13 84 psophomet rically weighted. pre/de - emphasis, compandor and 25khz channel filter selected. 85 av dd = 3.3v.
digital pmr (dpmr) baseband processor CMX8341 ? 9.2 operating characteristics C timing diagrams 9.2.1 c - bus timing figure 27 c - bus timing c - bus timing notes min. typ. max. unit t cse csn enable to sclk high time 100 C C ns t csh last sclk high to csn high time 100 C C ns t loz sclk low to rdata output enable time 0.0 C C ns t hiz csn high to rdata high impedance C C 1.0 s t csoff csn high time between transactions 1.0 C C s t nxt inter - byte time 200 C C ns t ck sclk cycle time 200 C C ns t ch sclk high time 100 C C ns t cl sclk low time 100 C C ns t cds cdata setup time 75 C C ns t cdh cdata hold time 25 C C ns t rds rdata setup time 50 C C ns t rdh rdata hold time 0 C C ns c - bus latency C 250 C s notes: 1. depending on the command, 1 or 2 bytes of cdata are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. rdata is read from the peripheral msb (bit 7) first, lsb (bit 0) last. 2. data is clock ed into the peripheral on the rising sclk edge. 3. commands are acted upon between the last rising edge of sclk of each command and the rising edge of the csn signal. 4. to allow for differing c serial interface formats c - bus compatible ics are able to work with sclk pulses starting and ending at either polarity. 5. maximum 30pf load on irqn pin and each c - bus interface line. these timings are for the latest version of c - bus and allow faster transfers than the original c - bus timing specification. the CMX8341 can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints.
digital pmr (dpmr) baseband processor CMX8341 ? 9.3 packaging figure 28 l8 mechanical outline: order as part no. CMX8341l8
digital pmr (dpmr) baseband processor CMX8341 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the s aid circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed. about firmasic ? cmls proprietary firmasic ? component technology reduces cost, time to market and development risk, with increased flexibility for the designer and end application. firmasic ? combines analogue, digital, fi rmware and memory technologies in a single silicon platform that can be focused to deliver the right feature mix, performance and price for a target application family. specific functions of a firmasic ? device are determined by uploading its function imag e? during device initialization. new function images? may be later provided to supplement and enhance device functions, expanding or modifying end - product features without the need for expensive and time - consuming design changes. firmasic ? devices provid e significant time to market and commercial benefits over custom asic, structured asic, fpga and dsp solutions. they may also be exclusively customised where security or intellectual property issues prevent the use of application specific standard products (assps).

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